Lines Matching defs:res
67 struct virgl_resource *res)
69 return res->b.nr_samples < 2 &&
70 vs->base.is_format_supported(&vs->base, res->b.format, res->b.target,
71 res->b.nr_samples, res->b.nr_samples,
76 struct virgl_resource *res,
81 virgl_has_scanout_format(vs, res->b.format, true);
85 struct virgl_resource *res)
88 (res->b.target != PIPE_BUFFER);
91 static bool is_stencil_array(struct virgl_resource *res)
93 const struct util_format_description *descr = util_format_description(res->b.format);
94 return (res->b.array_size > 1 || res->b.depth0 > 1) && util_format_has_stencil(descr);
98 struct virgl_resource *res,
101 return virgl_can_use_staging(vs, res) &&
102 !is_stencil_array(res) &&
103 virgl_has_readback_format(&vs->base, pipe_to_virgl_format(res->b.format), false) &&
105 virgl_can_readback_from_rendertarget(vs, res) ||
106 virgl_can_readback_from_scanout(vs, res, bind));
119 struct virgl_resource *res = virgl_resource(trans->base.resource);
124 if (!vws->res_is_referenced(vws, vctx->cbuf, res->hw_res))
141 struct virgl_resource *res,
148 if (res->clean_mask & (1 << level))
160 struct virgl_resource *res = virgl_resource(xfer->base.resource);
179 readback = virgl_res_needs_readback(vctx, res, xfer->base.usage,
191 if (res->b.target == PIPE_BUFFER &&
192 !util_ranges_intersect(&res->valid_buffer_range, xfer->base.box.x,
216 can_realloc = virgl_can_rebind_resource(vctx, &res->b);
226 wait = (flush || vws->resource_is_busy(vws, res->hw_res));
250 if (res->use_staging) {
275 (readback || (wait && vws->resource_is_busy(vws, res->hw_res))))
283 vws->resource_wait(vws, res->hw_res);
284 vws->transfer_get(vws, res->hw_res, &xfer->base.box, xfer->base.stride,
292 vws->resource_wait(vws, res->hw_res);
294 if (res->use_staging) {
436 virgl_resource_realloc(struct virgl_context *vctx, struct virgl_resource *res)
439 const struct pipe_resource *templ = &res->b;
446 int alloc_size = res->use_staging ? 1 : res->metadata.total_size;
464 vs->vws->resource_reference(vs->vws, &res->hw_res, NULL);
465 res->hw_res = hw_res;
470 util_range_set_empty(&res->valid_buffer_range);
473 vctx->queued_staging_res_size += res->metadata.total_size;
475 virgl_rebind_resource(vctx, &res->b);
640 struct virgl_resource *res = CALLOC_STRUCT(virgl_resource);
643 res->b = *templ;
644 res->b.screen = &vs->base;
645 pipe_reference_init(&res->b.reference, 1);
648 virgl_resource_layout(&res->b, &res->metadata, 0, 0, 0, 0);
662 res->use_staging = virgl_can_copy_transfer_from_host(vs, res, vbind);
664 if (res->use_staging)
667 alloc_size = res->metadata.total_size;
669 res->hw_res = vs->vws->resource_create(vs->vws, templ->target,
680 if (!res->hw_res) {
681 FREE(res);
685 res->clean_mask = (1 << VR_MAX_TEXTURE_2D_LEVELS) - 1;
688 util_range_init(&res->valid_buffer_range);
689 virgl_buffer_init(res);
691 virgl_texture_init(res);
694 return &res->b;
715 struct virgl_resource *res = CALLOC_STRUCT(virgl_resource);
716 res->b = *templ;
717 res->b.screen = &vs->base;
718 pipe_reference_init(&res->b.reference, 1);
721 res->hw_res = vs->vws->resource_create_from_handle(vs->vws, whandle,
726 &res->blob_mem);
729 if (!res->blob_mem) {
735 virgl_resource_layout(&res->b, &res->metadata, plane, winsys_stride,
737 if (!res->hw_res) {
738 FREE(res);
743 if (res->blob_mem && plane == 0 &&
748 struct pipe_resource *iter = &res->b;
759 plane->hw_res != res->hw_res ||
761 vs->vws->resource_reference(vs->vws, &res->hw_res, NULL);
762 FREE(res);
773 res->hw_res,
774 pipe_to_virgl_format(res->b.format),
775 pipe_to_virgl_bind(vs, res->b.bind),
776 res->b.width0,
777 res->b.height0,
779 res->metadata.modifier,
785 virgl_texture_init(res);
787 return &res->b;
912 struct virgl_resource *res = virgl_resource(resource);
914 if (res->b.target == PIPE_BUFFER)
915 util_range_destroy(&res->valid_buffer_range);
917 vs->vws->resource_reference(vs->vws, &res->hw_res, NULL);
918 FREE(res);
928 struct virgl_resource *res = virgl_resource(resource);
930 if (res->b.target == PIPE_BUFFER)
933 return vs->vws->resource_get_handle(vs->vws, res->hw_res,
934 res->metadata.stride[0],
938 void virgl_resource_dirty(struct virgl_resource *res, uint32_t level)
940 if (res) {
941 if (res->b.target == PIPE_BUFFER)
942 res->clean_mask &= ~1;
944 res->clean_mask &= ~(1 << level);