Lines Matching refs:state
433 const struct pipe_rasterizer_state *state)
440 tmp = VIRGL_OBJ_RS_S0_FLATSHADE(state->flatshade) |
441 VIRGL_OBJ_RS_S0_DEPTH_CLIP(state->depth_clip_near) |
442 VIRGL_OBJ_RS_S0_CLIP_HALFZ(state->clip_halfz) |
443 VIRGL_OBJ_RS_S0_RASTERIZER_DISCARD(state->rasterizer_discard) |
444 VIRGL_OBJ_RS_S0_FLATSHADE_FIRST(state->flatshade_first) |
445 VIRGL_OBJ_RS_S0_LIGHT_TWOSIZE(state->light_twoside) |
446 VIRGL_OBJ_RS_S0_SPRITE_COORD_MODE(state->sprite_coord_mode) |
447 VIRGL_OBJ_RS_S0_POINT_QUAD_RASTERIZATION(state->point_quad_rasterization) |
448 VIRGL_OBJ_RS_S0_CULL_FACE(state->cull_face) |
449 VIRGL_OBJ_RS_S0_FILL_FRONT(state->fill_front) |
450 VIRGL_OBJ_RS_S0_FILL_BACK(state->fill_back) |
451 VIRGL_OBJ_RS_S0_SCISSOR(state->scissor) |
452 VIRGL_OBJ_RS_S0_FRONT_CCW(state->front_ccw) |
453 VIRGL_OBJ_RS_S0_CLAMP_VERTEX_COLOR(state->clamp_vertex_color) |
454 VIRGL_OBJ_RS_S0_CLAMP_FRAGMENT_COLOR(state->clamp_fragment_color) |
455 VIRGL_OBJ_RS_S0_OFFSET_LINE(state->offset_line) |
456 VIRGL_OBJ_RS_S0_OFFSET_POINT(state->offset_point) |
457 VIRGL_OBJ_RS_S0_OFFSET_TRI(state->offset_tri) |
458 VIRGL_OBJ_RS_S0_POLY_SMOOTH(state->poly_smooth) |
459 VIRGL_OBJ_RS_S0_POLY_STIPPLE_ENABLE(state->poly_stipple_enable) |
460 VIRGL_OBJ_RS_S0_POINT_SMOOTH(state->point_smooth) |
461 VIRGL_OBJ_RS_S0_POINT_SIZE_PER_VERTEX(state->point_size_per_vertex) |
462 VIRGL_OBJ_RS_S0_MULTISAMPLE(state->multisample) |
463 VIRGL_OBJ_RS_S0_LINE_SMOOTH(state->line_smooth) |
464 VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
465 VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(state->line_last_pixel) |
466 VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(state->half_pixel_center) |
467 VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule) |
468 VIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(state->force_persample_interp);
471 virgl_encoder_write_dword(ctx->cbuf, fui(state->point_size)); /* S1 */
472 virgl_encoder_write_dword(ctx->cbuf, state->sprite_coord_enable); /* S2 */
473 tmp = VIRGL_OBJ_RS_S3_LINE_STIPPLE_PATTERN(state->line_stipple_pattern) |
474 VIRGL_OBJ_RS_S3_LINE_STIPPLE_FACTOR(state->line_stipple_factor) |
475 VIRGL_OBJ_RS_S3_CLIP_PLANE_ENABLE(state->clip_plane_enable);
477 virgl_encoder_write_dword(ctx->cbuf, fui(state->line_width)); /* S4 */
478 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_units)); /* S5 */
479 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_scale)); /* S6 */
480 virgl_encoder_write_dword(ctx->cbuf, fui(state->offset_clamp)); /* S7 */
668 const struct pipe_framebuffer_state *state)
670 struct virgl_surface *zsurf = virgl_surface(state->zsbuf);
673 virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_SET_FRAMEBUFFER_STATE, 0, VIRGL_SET_FRAMEBUFFER_STATE_SIZE(state->nr_cbufs)));
674 virgl_encoder_write_dword(ctx->cbuf, state->nr_cbufs);
676 for (i = 0; i < state->nr_cbufs; i++) {
677 struct virgl_surface *surf = virgl_surface(state->cbufs[i]);
684 virgl_encoder_write_dword(ctx->cbuf, state->width | (state->height << 16));
685 virgl_encoder_write_dword(ctx->cbuf, state->layers | (state->samples << 16));
954 const struct pipe_sampler_state *state)
961 tmp = VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_S(state->wrap_s) |
962 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_T(state->wrap_t) |
963 VIRGL_OBJ_SAMPLE_STATE_S0_WRAP_R(state->wrap_r) |
964 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_IMG_FILTER(state->min_img_filter) |
965 VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(state->min_mip_filter) |
966 VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(state->mag_img_filter) |
967 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(state->compare_mode) |
968 VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func) |
969 VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(state->seamless_cube_map) |
970 VIRGL_OBJ_SAMPLE_STATE_S0_MAX_ANISOTROPY((int)(state->max_anisotropy));
973 virgl_encoder_write_dword(ctx->cbuf, fui(state->lod_bias));
974 virgl_encoder_write_dword(ctx->cbuf, fui(state->min_lod));
975 virgl_encoder_write_dword(ctx->cbuf, fui(state->max_lod));
977 virgl_encoder_write_dword(ctx->cbuf, state->border_color.ui[i]);
985 const struct pipe_sampler_view *state)
987 unsigned elem_size = util_format_get_blocksize(state->format);
990 uint32_t dword_fmt_target = pipe_to_virgl_format(state->format);
995 dword_fmt_target |= (state->target << 24);
998 virgl_encoder_write_dword(ctx->cbuf, state->u.buf.offset / elem_size);
999 virgl_encoder_write_dword(ctx->cbuf, (state->u.buf.offset + state->u.buf.size) / elem_size - 1);
1002 assert(state->u.tex.first_layer == 0 && state->u.tex.last_layer == 0);
1005 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_layer | state->u.tex.last_layer << 16);
1007 virgl_encoder_write_dword(ctx->cbuf, state->u.tex.first_level | state->u.tex.last_level << 8);
1009 tmp = VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_R(state->swizzle_r) |
1010 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_G(state->swizzle_g) |
1011 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_B(state->swizzle_b) |
1012 VIRGL_OBJ_SAMPLER_VIEW_SWIZZLE_A(state->swizzle_a);