Lines Matching refs:so
10 * Software is furnished to do so, subject to the following conditions:
97 struct vc4_rasterizer_state *so;
102 so = CALLOC_STRUCT(vc4_rasterizer_state);
103 if (!so)
106 so->base = *cso;
109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT;
111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK;
121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES;
124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET;
133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X;
135 V3D21_DEPTH_OFFSET_pack(NULL, so->packed.depth_offset, &depth_offset);
136 V3D21_POINT_SIZE_pack(NULL, so->packed.point_size, &point_size);
137 V3D21_LINE_WIDTH_pack(NULL, so->packed.line_width, &line_width);
140 so->tile_raster_order_flags |= VC4_SUBMIT_CL_FIXED_RCL_ORDER;
142 so->tile_raster_order_flags |=
146 so->tile_raster_order_flags |=
151 return so;
164 * values, so you don't have to do a separate writemask setup.
210 struct vc4_depth_stencil_alpha_state *so;
212 so = CALLOC_STRUCT(vc4_depth_stencil_alpha_state);
213 if (!so)
216 so->base = *cso;
221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE;
225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE;
227 so->config_bits[1] |= (cso->depth_func <<
240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z;
243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS <<
256 so->stencil_uniforms[0] =
263 so->stencil_uniforms[0] |= (1 << 30);
264 so->stencil_uniforms[1] =
266 so->stencil_uniforms[1] |= (2 << 30);
268 so->stencil_uniforms[0] |= (3 << 30);
273 so->stencil_uniforms[2] = (front->writemask |
278 return so;
321 struct vc4_vertexbuf_stateobj *so = &vc4->vertexbuf;
323 util_set_vertex_buffers_mask(so->vb, &so->enabled_mask, vb,
327 so->count = util_last_bit(so->enabled_mask);
367 struct vc4_vertex_stateobj *so = CALLOC_STRUCT(vc4_vertex_stateobj);
369 if (!so)
372 memcpy(so->pipe, elements, sizeof(*elements) * num_elements);
373 so->num_elements = num_elements;
375 return so;
393 struct vc4_constbuf_stateobj *so = &vc4->constbuf[shader];
399 so->enabled_mask &= ~(1 << index);
400 so->dirty_mask &= ~(1 << index);
404 if (index == 1 && so->cb[index].buffer_size != cb->buffer_size)
407 util_copy_constant_buffer(&so->cb[index], cb, take_ownership);
409 so->enabled_mask |= 1 << index;
410 so->dirty_mask |= 1 << index;
427 * stride from the width parameter, so we need to configure our
505 struct vc4_sampler_state *so = CALLOC_STRUCT(vc4_sampler_state);
507 if (!so)
510 memcpy(so, cso, sizeof(*cso));
512 so->texture_p1 =
523 return so;
555 struct vc4_sampler_view *so = CALLOC_STRUCT(vc4_sampler_view);
558 if (!so)
561 so->base = *cso;
563 so->base.texture = NULL;
564 pipe_resource_reference(&so->base.texture, prsc);
565 so->base.reference.count = 1;
566 so->base.context = pctx;
569 * texture may be misaligned, so in that case we have to copy to a
573 * so we also have to copy to a temporary then.
597 free(so);
609 so->texture = prsc;
611 pipe_resource_reference(&so->texture, prsc);
614 so->force_first_level = true;
618 so->texture_p0 =
623 VC4_SET_FIELD(so->force_first_level ?
629 so->texture_p1 =
635 so->texture_p1 |= VC4_TEX_P1_ETCFLIP_MASK;
637 return &so->base;