Lines Matching defs:instr
269 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
272 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
273 unsigned chan = ffs(instr->dest.write_mask) - 1;
274 struct qreg r = ntq_get_src(c, instr->src[src].src,
275 instr->src[src].swizzle[chan]);
277 assert(!instr->src[src].abs);
278 assert(!instr->src[src].negate);
352 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
359 unsigned unit = instr->texture_index;
367 assert(instr->num_srcs == 1);
368 assert(instr->src[0].src_type == nir_tex_src_coord);
369 addr = ntq_get_src(c, instr->src[0].src, 0);
387 ntq_store_dest(c, &instr->dest, i, qir_MOV(c, scaled));
390 ntq_store_dest(c, &instr->dest, i,
396 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
400 unsigned unit = instr->texture_index;
402 if (instr->op == nir_texop_txf) {
403 ntq_emit_txf(c, instr);
407 for (unsigned i = 0; i < instr->num_srcs; i++) {
408 switch (instr->src[i].src_type) {
410 s = ntq_get_src(c, instr->src[i].src, 0);
411 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
414 t = ntq_get_src(c, instr->src[i].src, 1);
415 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
416 r = ntq_get_src(c, instr->src[i].src, 2);
419 lod = ntq_get_src(c, instr->src[i].src, 0);
423 lod = ntq_get_src(c, instr->src[i].src, 0);
427 compare = ntq_get_src(c, instr->src[i].src, 0);
458 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
464 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
561 ntq_store_dest(c, &instr->dest, i,
565 ntq_store_dest(c, &instr->dest, i,
823 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
831 if (instr->src[0].src.is_ssa &&
832 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
833 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
835 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
842 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
843 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
844 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
846 instr->src[0].src,
847 instr->src[0].swizzle[0]);
848 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
853 int swiz = instr->src[0].swizzle[i];
859 src = ntq_get_src(c, instr->src[0].src, swiz);
878 ntq_store_dest(c, &instr->dest.dest, 0, qir_MOV(c, result));
995 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
998 if (!instr->src[0].src.is_ssa)
1000 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
1003 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
1008 if (ntq_emit_comparison(c, &dest, compare, instr))
1057 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
1060 assert(!instr->dest.saturate);
1066 if (instr->op == nir_op_vec2 ||
1067 instr->op == nir_op_vec3 ||
1068 instr->op == nir_op_vec4) {
1070 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1071 srcs[i] = ntq_get_src(c, instr->src[i].src,
1072 instr->src[i].swizzle[0]);
1073 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1074 ntq_store_dest(c, &instr->dest.dest, i,
1079 if (instr->op == nir_op_pack_unorm_4x8) {
1080 ntq_emit_pack_unorm_4x8(c, instr);
1084 if (instr->op == nir_op_unpack_unorm_4x8) {
1085 struct qreg src = ntq_get_src(c, instr->src[0].src,
1086 instr->src[0].swizzle[0]);
1088 if (instr->dest.write_mask & (1 << i))
1089 ntq_store_dest(c, &instr->dest.dest, i,
1096 struct qreg src[nir_op_infos[instr->op].num_inputs];
1097 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1098 src[i] = ntq_get_alu_src(c, instr, i);
1103 switch (instr->op) {
1196 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1202 result = ntq_emit_bcsel(c, instr, src);
1296 nir_print_instr(&instr->instr, stderr);
1304 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1305 ntq_store_dest(c, &instr->dest.dest,
1306 ffs(instr->dest.write_mask) - 1, result);
1654 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1656 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1657 for (int i = 0; i < instr->def.num_components; i++)
1658 qregs[i] = qir_uniform_ui(c, instr->value[i].u32);
1660 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1664 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1666 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1671 for (int i = 0; i < instr->def.num_components; i++)
1676 ntq_emit_color_read(struct vc4_compile *c, nir_intrinsic_instr *instr)
1678 assert(nir_src_as_uint(instr->src[0]) == 0);
1683 int sample_index = (nir_intrinsic_base(instr) -
1691 ntq_store_dest(c, &instr->dest, 0,
1696 ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
1698 assert(instr->num_components == 1);
1699 assert(nir_src_is_const(instr->src[0]) &&
1703 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1704 ntq_emit_color_read(c, instr);
1708 uint32_t offset = nir_intrinsic_base(instr) +
1709 nir_src_as_uint(instr->src[0]);
1710 int comp = nir_intrinsic_component(instr);
1711 ntq_store_dest(c, &instr->dest, 0,
1716 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1720 switch (instr->intrinsic) {
1722 assert(instr->num_components == 1);
1723 if (nir_src_is_const(instr->src[0])) {
1724 offset = nir_intrinsic_base(instr) +
1725 nir_src_as_uint(instr->src[0]);
1729 ntq_store_dest(c, &instr->dest, 0,
1733 ntq_store_dest(c, &instr->dest, 0,
1734 indirect_uniform_load(c, instr));
1739 assert(instr->num_components == 1);
1740 ntq_store_dest(c, &instr->dest, 0, vc4_ubo_load(c, instr));
1744 for (int i = 0; i < nir_intrinsic_dest_components(instr); i++) {
1745 ntq_store_dest(c, &instr->dest, i,
1747 nir_intrinsic_ucp_id(instr) *
1756 ntq_store_dest(c, &instr->dest, 0,
1758 (instr->intrinsic -
1764 ntq_store_dest(c, &instr->dest, 0,
1770 ntq_store_dest(c, &instr->dest, 0,
1776 ntq_store_dest(c, &instr->dest, 0,
1784 ntq_store_dest(c, &instr->dest, 0,
1791 ntq_emit_load_input(c, instr);
1795 assert(nir_src_is_const(instr->src[1]) &&
1797 offset = nir_intrinsic_base(instr) +
1798 nir_src_as_uint(instr->src[1]);
1804 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1808 qir_MOV(c, ntq_get_src(c, instr->src[0],
1812 offset = offset * 4 + nir_intrinsic_component(instr);
1813 assert(instr->num_components == 1);
1815 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1832 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1843 ntq_get_src(c, instr->src[0], 0));
1850 assert(nir_src_is_const(instr->src[0]));
1851 int sampler = nir_src_as_int(instr->src[0]);
1853 ntq_store_dest(c, &instr->dest, 0,
1855 ntq_store_dest(c, &instr->dest, 1,
1862 nir_print_instr(&instr->instr, stderr);
1990 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
1992 switch (instr->type) {
1994 ntq_emit_alu(c, nir_instr_as_alu(instr));
1998 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2002 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2006 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2010 ntq_emit_tex(c, nir_instr_as_tex(instr));
2014 ntq_emit_jump(c, nir_instr_as_jump(instr));
2018 fprintf(stderr, "Unknown NIR instr type: ");
2019 nir_print_instr(instr, stderr);
2028 nir_foreach_instr(instr, block) {
2029 ntq_emit_instr(c, instr);
2197 nir_foreach_instr(instr, block)