Lines Matching refs:store
40 * dummy store.
49 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
50 store.buffer_to_store = NONE;
98 /* Can't do raw ZSTENCIL loads -- need to load/store them to
137 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
138 store.buffer_to_store = buffer;
139 store.address = cl_address(rsc->bo, layer_offset);
142 store.clear_buffer_being_stored = false;
145 store.output_image_format = V3D_OUTPUT_IMAGE_FORMAT_S8;
147 store.output_image_format = surf->format;
149 store.r_b_swap = surf->swap_rb;
150 store.memory_format = surf->tiling;
154 store.height_in_ub_or_stride =
159 store.height_in_ub_or_stride = slice->stride;
164 store.decimate_mode = V3D_DECIMATE_MODE_ALL_SAMPLES;
166 store.decimate_mode = V3D_DECIMATE_MODE_4X;
168 store.decimate_mode = V3D_DECIMATE_MODE_SAMPLE_0;
171 /* Can't do raw ZSTENCIL stores -- need to load/store them to
175 store.raw_mode = true;
177 store.disable_color_buffers_clear_on_write = true;
178 store.disable_z_buffer_clear_on_write = true;
179 store.disable_stencil_buffer_clear_on_write = true;
181 store.disable_color_buffers_clear_on_write =
185 store.disable_z_buffer_clear_on_write =
187 store.disable_stencil_buffer_clear_on_write =
190 store.padded_height_of_output_image_in_uif_blocks =
195 /* There must be a TILE_COORDINATES_IMPLICIT between each store. */
226 uint32_t loads_pending = job->bbuf ? job->store : job->load;
301 * - NONE buffer store clears all TLB color buffers.
302 * - color buffer store clears just the TLB color buffer being stored.
303 * - Z/S buffers store may not clear the TLB color buffer.
315 (job->store & PIPE_CLEAR_COLOR_BUFFERS));
320 uint32_t stores_pending = job->store;
334 if (!(job->store & bit))
347 if (job->store & PIPE_CLEAR_DEPTHSTENCIL && job->zsbuf &&
352 if (job->store & PIPE_CLEAR_DEPTH) {
360 if (job->store & PIPE_CLEAR_STENCIL) {
369 zs_buffer_from_pipe_bits(job->store),
370 job->store & PIPE_CLEAR_DEPTHSTENCIL,
378 cl_emit(cl, STORE_MULTI_SAMPLE_RESOLVED_TILE_COLOR_BUFFER_EXTENDED, store) {
380 store.disable_color_buffer_write =
383 store.enable_z_write = stores_pending & PIPE_CLEAR_DEPTH;
384 store.enable_stencil_write = stores_pending & PIPE_CLEAR_STENCIL;
389 store.disable_color_buffers_clear_on_write =
391 store.disable_z_buffer_clear_on_write =
393 store.disable_stencil_buffer_clear_on_write =
400 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
401 store.buffer_to_store = NONE;
406 * we still need to emit some sort of store.
408 if (!job->store) {
409 cl_emit(cl, STORE_TILE_BUFFER_GENERAL, store) {
410 store.buffer_to_store = NONE;
416 /* GFXH-1461/GFXH-1689: The per-buffer store command's clear
451 * the stores go. There must be one per store packet.
527 if (job->store & (is_separate_stencil ?
645 * state, we need 1 dummy store in between internal type/size
649 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
650 store.buffer_to_store = NONE;
657 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
658 store.buffer_to_store = NONE;
722 config.enable_z_store = job->store & PIPE_CLEAR_DEPTH;
723 config.enable_stencil_store = job->store & PIPE_CLEAR_STENCIL;
757 !(job->store & PIPE_CLEAR_DEPTHSTENCIL);
810 if (job->store & PIPE_CLEAR_COLOR0 << i)
876 * it. The HW will only load/store this buffer if the
905 * shaders can still do image load/store, ssbo, etc without having to
909 assert(job->num_layers > 0 || (job->load == 0 && job->store == 0));