Lines Matching refs:job
114 store_general(struct v3d_job *job,
162 assert(!resolve_4x || job->bbuf);
165 else if (resolve_4x && job->bbuf->texture->nr_samples > 1)
184 (job->clear & pipe_bit)));
186 !(job->clear & PIPE_CLEAR_DEPTH);
188 !(job->clear & PIPE_CLEAR_STENCIL);
217 v3d_rcl_emit_loads(struct v3d_job *job, struct v3d_cl *cl, int layer)
222 assert(!job->bbuf || job->load == 0);
223 assert(!job->bbuf || job->nr_cbufs <= 1);
224 assert(!job->bbuf || V3D_VERSION >= 40);
226 uint32_t loads_pending = job->bbuf ? job->store : job->load;
228 for (int i = 0; i < job->nr_cbufs; i++) {
233 struct pipe_surface *psurf = job->bbuf ? job->bbuf : job->cbufs[i];
234 assert(!job->bbuf || i == 0);
247 (job->zsbuf && job->zsbuf->texture->nr_samples > 1))) {
248 assert(!job->early_zs_clear);
249 struct pipe_surface *src = job->bbuf ? job->bbuf : job->zsbuf;
292 v3d_rcl_emit_stores(struct v3d_job *job, struct v3d_cl *cl, int layer)
295 UNUSED bool needs_color_clear = job->clear & PIPE_CLEAR_COLOR_BUFFERS;
296 UNUSED bool needs_z_clear = job->clear & PIPE_CLEAR_DEPTH;
297 UNUSED bool needs_s_clear = job->clear & PIPE_CLEAR_STENCIL;
314 (job->clear & PIPE_CLEAR_COLOR_BUFFERS) ==
315 (job->store & PIPE_CLEAR_COLOR_BUFFERS));
320 uint32_t stores_pending = job->store;
331 assert(!job->bbuf || job->nr_cbufs <= 1);
332 for (int i = 0; i < job->nr_cbufs; i++) {
334 if (!(job->store & bit))
337 struct pipe_surface *psurf = job->cbufs[i];
343 store_general(job, cl, psurf, layer, RENDER_TARGET_0 + i, bit,
344 &stores_pending, general_color_clear, job->bbuf);
347 if (job->store & PIPE_CLEAR_DEPTHSTENCIL && job->zsbuf &&
348 !(V3D_VERSION < 40 && job->zsbuf->texture->nr_samples <= 1)) {
349 assert(!job->early_zs_clear);
350 struct v3d_resource *rsc = v3d_resource(job->zsbuf->texture);
352 if (job->store & PIPE_CLEAR_DEPTH) {
353 store_general(job, cl, job->zsbuf, layer,
360 if (job->store & PIPE_CLEAR_STENCIL) {
361 store_general(job, cl, job->zsbuf, layer,
368 store_general(job, cl, job->zsbuf, layer,
369 zs_buffer_from_pipe_bits(job->store),
370 job->store & PIPE_CLEAR_DEPTHSTENCIL,
408 if (!job->store) {
421 if (job->clear) {
423 clear.clear_z_stencil_buffer = !job->early_zs_clear;
431 v3d_rcl_emit_generic_per_tile_list(struct v3d_job *job, int layer)
436 struct v3d_cl *cl = &job->indirect;
447 v3d_rcl_emit_loads(job, cl, layer);
472 v3d_rcl_emit_stores(job, cl, layer);
480 cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) {
488 v3d_setup_render_target(struct v3d_job *job, int cbuf,
491 if (!job->cbufs[cbuf])
494 struct v3d_surface *surf = v3d_surface(job->cbufs[cbuf]);
496 if (job->bbuf) {
497 struct v3d_surface *bsurf = v3d_surface(job->bbuf);
507 v3d_emit_z_stencil_config(struct v3d_job *job, struct v3d_surface *surf,
510 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_Z_STENCIL, zs) {
527 if (job->store & (is_separate_stencil ?
538 supertile_in_job_scissors(struct v3d_job *job,
541 if (job->scissor.disabled || job->scissor.count == 0)
549 for (uint32_t i = 0; i < job->scissor.count; i++) {
550 const uint32_t min_s_x = job->scissor.rects[i].min_x;
551 const uint32_t min_s_y = job->scissor.rects[i].min_y;
552 const uint32_t max_s_x = job->scissor.rects[i].max_x;
553 const uint32_t max_s_y = job->scissor.rects[i].max_y;
568 do_double_initial_tile_clear(const struct v3d_job *job)
578 return job->double_buffer &&
579 (job->draw_tiles_x > 1 || job->draw_tiles_y > 1);
584 emit_render_layer(struct v3d_job *job, uint32_t layer)
592 layer * job->draw_tiles_x * job->draw_tiles_y * 64;
593 cl_emit(&job->rcl, MULTICORE_RENDERING_TILE_LIST_SET_BASE, list) {
594 list.address = cl_address(job->tile_alloc, tile_alloc_offset);
597 cl_emit(&job->rcl, MULTICORE_RENDERING_SUPERTILE_CFG, config) {
603 frame_w_in_supertiles = div_round_up(job->draw_tiles_x,
605 frame_h_in_supertiles = div_round_up(job->draw_tiles_y,
619 config.total_frame_width_in_tiles = job->draw_tiles_x;
620 config.total_frame_height_in_tiles = job->draw_tiles_y;
630 cl_emit(&job->rcl, TILE_COORDINATES, coords) {
649 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
655 cl_emit(&job->rcl, TILE_COORDINATES, coords);
656 cl_emit(&job->rcl, END_OF_LOADS, end);
657 cl_emit(&job->rcl, STORE_TILE_BUFFER_GENERAL, store) {
660 if (i == 0 || do_double_initial_tile_clear(job)) {
661 cl_emit(&job->rcl, CLEAR_TILE_BUFFERS, clear) {
662 clear.clear_z_stencil_buffer = !job->early_zs_clear;
666 cl_emit(&job->rcl, END_OF_TILE_MARKER, end);
670 cl_emit(&job->rcl, FLUSH_VCD_CACHE, flush);
672 v3d_rcl_emit_generic_per_tile_list(job, layer);
678 uint32_t supertile_w_in_pixels = job->tile_width * supertile_w;
679 uint32_t supertile_h_in_pixels = job->tile_height * supertile_h;
680 uint32_t min_x_supertile = job->draw_min_x / supertile_w_in_pixels;
681 uint32_t min_y_supertile = job->draw_min_y / supertile_h_in_pixels;
685 if (job->draw_max_x != 0 && job->draw_max_y != 0) {
686 max_x_supertile = (job->draw_max_x - 1) / supertile_w_in_pixels;
687 max_y_supertile = (job->draw_max_y - 1) / supertile_h_in_pixels;
692 if (supertile_in_job_scissors(job, x, y,
695 cl_emit(&job->rcl, SUPERTILE_COORDINATES, coords) {
705 v3dX(emit_rcl)(struct v3d_job *job)
708 assert(!job->rcl.bo);
710 v3d_cl_ensure_space_with_branch(&job->rcl, 200 +
711 MAX2(job->num_layers, 1) * 256 *
713 job->submit.rcl_start = job->rcl.bo->offset;
714 v3d_job_add_bo(job, job->rcl.bo);
720 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COMMON, config) {
722 config.enable_z_store = job->store & PIPE_CLEAR_DEPTH;
723 config.enable_stencil_store = job->store & PIPE_CLEAR_STENCIL;
725 if (job->zsbuf) {
726 struct v3d_surface *surf = v3d_surface(job->zsbuf);
731 if (job->decided_global_ez_enable) {
732 switch (job->first_ez_state) {
748 assert(job->draw_calls_queued == 0);
753 assert(job->zsbuf || config.early_z_disable);
755 job->early_zs_clear = (job->clear & PIPE_CLEAR_DEPTHSTENCIL) &&
756 !(job->load & PIPE_CLEAR_DEPTHSTENCIL) &&
757 !(job->store & PIPE_CLEAR_DEPTHSTENCIL);
759 config.early_depth_stencil_clear = job->early_zs_clear;
762 config.image_width_pixels = job->draw_width;
763 config.image_height_pixels = job->draw_height;
765 config.number_of_render_targets = MAX2(job->nr_cbufs, 1);
767 assert(!job->msaa || !job->double_buffer);
768 config.multisample_mode_4x = job->msaa;
769 config.double_buffer_in_non_ms_mode = job->double_buffer;
771 config.maximum_bpp_of_all_render_targets = job->internal_bpp;
774 for (int i = 0; i < job->nr_cbufs; i++) {
775 struct pipe_surface *psurf = job->cbufs[i];
788 uint32_t implicit_padded_height = (align(job->draw_height, uif_block_height) /
801 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
810 if (job->store & PIPE_CLEAR_COLOR0 << i)
815 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART1,
817 clear.clear_color_low_32_bits = job->clear_color[i][0];
818 clear.clear_color_next_24_bits = job->clear_color[i][1] & 0xffffff;
823 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART2,
826 ((job->clear_color[i][1] >> 24) |
827 (job->clear_color[i][2] << 8));
829 ((job->clear_color[i][2] >> 24) |
830 ((job->clear_color[i][3] & 0xffff) << 8));
836 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_CLEAR_COLORS_PART3,
839 clear.clear_color_high_16_bits = job->clear_color[i][3] >> 16;
846 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_COLOR, rt) {
847 v3d_setup_render_target(job, 0,
851 v3d_setup_render_target(job, 1,
855 v3d_setup_render_target(job, 2,
859 v3d_setup_render_target(job, 3,
868 if (job->zsbuf) {
869 struct pipe_surface *psurf = job->zsbuf;
873 v3d_emit_z_stencil_config(job, surf, rsc, false);
880 v3d_emit_z_stencil_config(job,
888 cl_emit(&job->rcl, TILE_RENDERING_MODE_CFG_ZS_CLEAR_VALUES,
890 clear.z_clear_value = job->clear_z;
891 clear.stencil_clear_value = job->clear_s;
897 cl_emit(&job->rcl, TILE_LIST_INITIAL_BLOCK_SIZE, init) {
909 assert(job->num_layers > 0 || (job->load == 0 && job->store == 0));
910 for (int layer = 0; layer < MAX2(1, job->num_layers); layer++)
911 emit_render_layer(job, layer);
913 cl_emit(&job->rcl, END_OF_RENDERING, end);