Lines Matching refs:tex
131 static unsigned si_texture_get_offset(struct si_screen *sscreen, struct si_texture *tex,
137 if (tex->surface.is_linear) {
138 pitch = tex->surface.u.gfx9.pitch[level];
140 pitch = tex->surface.u.gfx9.surf_pitch;
143 *stride = pitch * tex->surface.bpe;
144 *layer_stride = tex->surface.u.gfx9.surf_slice_size;
151 return tex->surface.u.gfx9.surf_offset + box->z * tex->surface.u.gfx9.surf_slice_size +
152 tex->surface.u.gfx9.offset[level] +
153 (box->y / tex->surface.blk_h * pitch + box->x / tex->surface.blk_w) *
154 tex->surface.bpe;
156 *stride = tex->surface.u.legacy.level[level].nblk_x * tex->surface.bpe;
157 assert((uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
158 *layer_stride = (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4;
161 return (uint64_t)tex->surface.u.legacy.level[level].offset_256B * 256;
165 return (uint64_t)tex->surface.u.legacy.level[level].offset_256B * 256 +
166 box->z * (uint64_t)tex->surface.u.legacy.level[level].slice_size_dw * 4 +
167 (box->y / tex->surface.blk_h * tex->surface.u.legacy.level[level].nblk_x +
168 box->x / tex->surface.blk_w) *
169 tex->surface.bpe;
324 void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex,
330 ctx->flush_resource(ctx, &tex->buffer.b.b);
343 void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex)
345 if (!tex->cmask_buffer)
348 assert(tex->buffer.b.b.nr_samples <= 1);
351 tex->cmask_base_address_reg = tex->buffer.gpu_address >> 8;
352 tex->dirty_level_mask = 0;
354 tex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
356 if (tex->cmask_buffer != &tex->buffer)
357 si_resource_reference(&tex->cmask_buffer, NULL);
359 tex->cmask_buffer = NULL;
366 static bool si_can_disable_dcc(struct si_texture *tex)
369 return !tex->is_depth &&
370 tex->surface.meta_offset &&
371 (!tex->buffer.b.is_shared ||
372 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE)) &&
373 !ac_modifier_has_dcc(tex->surface.modifier);
376 static bool si_texture_discard_dcc(struct si_screen *sscreen, struct si_texture *tex)
378 if (!si_can_disable_dcc(tex))
382 ac_surface_zero_dcc_fields(&tex->surface);
410 bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex)
415 return si_texture_discard_dcc(sscreen, tex);
417 if (!si_can_disable_dcc(tex))
421 si_decompress_dcc(sctx, tex);
424 return si_texture_discard_dcc(sscreen, tex);
427 static void si_reallocate_texture_inplace(struct si_context *sctx, struct si_texture *tex,
432 struct pipe_resource templ = tex->buffer.b.b;
437 if (tex->buffer.b.is_shared || tex->num_planes > 1)
441 if (tex->surface.is_linear)
462 i, 0, 0, 0, &tex->buffer.b.b, i, &box);
467 si_texture_discard_cmask(sctx->screen, tex);
468 si_texture_discard_dcc(sctx->screen, tex);
471 /* Replace the structure fields of tex. */
472 tex->buffer.b.b.bind = templ.bind;
473 radeon_bo_reference(sctx->screen->ws, &tex->buffer.buf, new_tex->buffer.buf);
474 tex->buffer.gpu_address = new_tex->buffer.gpu_address;
475 tex->buffer.memory_usage_kb = new_tex->buffer.memory_usage_kb;
476 tex->buffer.bo_size = new_tex->buffer.bo_size;
477 tex->buffer.bo_alignment_log2 = new_tex->buffer.bo_alignment_log2;
478 tex->buffer.domains = new_tex->buffer.domains;
479 tex->buffer.flags = new_tex->buffer.flags;
481 tex->surface = new_tex->surface;
482 si_texture_reference(&tex->flushed_depth_texture, new_tex->flushed_depth_texture);
484 tex->surface.fmask_offset = new_tex->surface.fmask_offset;
485 tex->surface.cmask_offset = new_tex->surface.cmask_offset;
486 tex->cmask_base_address_reg = new_tex->cmask_base_address_reg;
488 if (tex->cmask_buffer == &tex->buffer)
489 tex->cmask_buffer = NULL;
491 si_resource_reference(&tex->cmask_buffer, NULL);
494 tex->cmask_buffer = &tex->buffer;
496 si_resource_reference(&tex->cmask_buffer, new_tex->cmask_buffer);
498 tex->surface.meta_offset = new_tex->surface.meta_offset;
499 tex->cb_color_info = new_tex->cb_color_info;
500 memcpy(tex->color_clear_value, new_tex->color_clear_value, sizeof(tex->color_clear_value));
501 tex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
503 memcpy(tex->depth_clear_value, new_tex->depth_clear_value, sizeof(tex->depth_clear_value));
504 tex->dirty_level_mask = new_tex->dirty_level_mask;
505 tex->stencil_dirty_level_mask = new_tex->stencil_dirty_level_mask;
506 tex->db_render_format = new_tex->db_render_format;
507 memcpy(tex->stencil_clear_value, new_tex->stencil_clear_value, sizeof(tex->stencil_clear_value));
508 tex->tc_compatible_htile = new_tex->tc_compatible_htile;
509 tex->depth_cleared_level_mask_once = new_tex->depth_cleared_level_mask_once;
510 tex->stencil_cleared_level_mask_once = new_tex->stencil_cleared_level_mask_once;
511 tex->upgraded_depth = new_tex->upgraded_depth;
512 tex->db_compatible = new_tex->db_compatible;
513 tex->can_sample_z = new_tex->can_sample_z;
514 tex->can_sample_s = new_tex->can_sample_s;
516 tex->displayable_dcc_dirty = new_tex->displayable_dcc_dirty;
519 assert(!tex->surface.meta_offset);
520 assert(!tex->cmask_buffer);
521 assert(!tex->surface.fmask_size);
522 assert(!tex->is_depth);
530 static void si_set_tex_bo_metadata(struct si_screen *sscreen, struct si_texture *tex)
532 struct pipe_resource *res = &tex->buffer.b.b;
537 assert(tex->surface.fmask_size == 0);
544 sscreen->make_texture_descriptor(sscreen, tex, true, res->target, res->format, swizzle, 0,
547 si_set_mutable_tex_desc_fields(sscreen, tex, &tex->surface.u.legacy.level[0], 0, 0,
548 tex->surface.blk_w, false, 0, desc);
550 ac_surface_get_umd_metadata(&sscreen->info, &tex->surface,
551 tex->buffer.b.b.last_level + 1,
553 sscreen->ws->buffer_set_metadata(sscreen->ws, tex->buffer.buf, &md, &tex->surface);
556 static bool si_displayable_dcc_needs_explicit_flush(struct si_texture *tex)
558 struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen;
565 if (ac_surface_get_nplanes(&tex->surface) > 1)
568 return tex->surface.is_displayable && tex->surface.meta_offset;
583 struct si_texture *tex = (struct si_texture *)resource;
590 else if (tex->num_planes > 1)
591 *value = tex->num_planes;
593 *value = ac_surface_get_nplanes(&tex->surface);
601 &tex->surface, plane, level);
608 uint64_t level_offset = tex->surface.is_linear ? tex->surface.u.gfx9.offset[level] : 0;
610 &tex->surface, plane, layer) + level_offset;
615 *value = tex->surface.modifier;
664 struct si_texture *tex = (struct si_texture *)resource;
683 tex = (struct si_texture *)resource;
688 if (resource->nr_samples > 1 || tex->is_depth) {
694 whandle->size = tex->buffer.bo_size;
700 &tex->surface, plane, 0);
702 &tex->surface, plane, 0);
703 whandle->modifier = tex->surface.modifier;
708 if (sscreen->ws->buffer_is_suballocated(res->buf) || tex->surface.tile_swizzle ||
709 (tex->buffer.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
712 si_reallocate_texture_inplace(sctx, tex, PIPE_BIND_SHARED, false);
717 assert(tex->surface.tile_swizzle == 0);
725 (usage & PIPE_HANDLE_USAGE_SHADER_WRITE && !tex->is_depth && tex->surface.meta_offset) ||
728 si_displayable_dcc_needs_explicit_flush(tex))) {
729 if (si_texture_disable_dcc(sctx, tex)) {
737 (tex->cmask_buffer || (!tex->is_depth && tex->surface.meta_offset))) {
740 si_eliminate_fast_color_clear(sctx, tex, &flushed);
747 if (tex->cmask_buffer)
748 si_texture_discard_cmask(sscreen, tex);
753 si_set_tex_bo_metadata(sscreen, tex);
756 slice_size = tex->surface.u.gfx9.surf_slice_size;
758 slice_size = (uint64_t)tex->surface.u.legacy.level[0].slice_size_dw * 4;
761 modifier = tex->surface.modifier;
769 (tex->buffer.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
827 void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
839 tex->buffer.b.b.width0, tex->buffer.b.b.height0,
840 tex->buffer.b.b.depth0, tex->buffer.b.b.array_size,
841 tex->buffer.b.b.last_level, tex->buffer.b.b.nr_samples);
843 if (tex->is_depth && tex->surface.meta_offset)
844 u_log_printf(log, ", tc_compatible_htile=%u", tex->tc_compatible_htile);
847 util_format_short_name(tex->buffer.b.b.format));
852 ac_surface_print_info(f, &sscreen->info, &tex->surface);
861 if (!tex->is_depth && tex->surface.meta_offset) {
862 for (i = 0; i <= tex->buffer.b.b.last_level; i++)
866 i, i < tex->surface.num_meta_levels, tex->surface.u.legacy.color.dcc_level[i].dcc_offset,
867 tex->surface.u.legacy.color.dcc_level[i].dcc_fast_clear_size);
870 for (i = 0; i <= tex->buffer.b.b.last_level; i++)
875 i, (uint64_t)tex->surface.u.legacy.level[i].offset_256B * 256,
876 (uint64_t)tex->surface.u.legacy.level[i].slice_size_dw * 4,
877 u_minify(tex->buffer.b.b.width0, i), u_minify(tex->buffer.b.b.height0, i),
878 u_minify(tex->buffer.b.b.depth0, i), tex->surface.u.legacy.level[i].nblk_x,
879 tex->surface.u.legacy.level[i].nblk_y, tex->surface.u.legacy.level[i].mode,
880 tex->surface.u.legacy.tiling_index[i]);
882 if (tex->surface.has_stencil) {
883 for (i = 0; i <= tex->buffer.b.b.last_level; i++) {
889 i, (uint64_t)tex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256,
890 (uint64_t)tex->surface.u.legacy.zs.stencil_level[i].slice_size_dw * 4,
891 u_minify(tex->buffer.b.b.width0, i), u_minify(tex->buffer.b.b.height0, i),
892 u_minify(tex->buffer.b.b.depth0, i),
893 tex->surface.u.legacy.zs.stencil_level[i].nblk_x,
894 tex->surface.u.legacy.zs.stencil_level[i].nblk_y,
895 tex->surface.u.legacy.zs.stencil_level[i].mode,
896 tex->surface.u.legacy.zs.stencil_tiling_index[i]);
921 struct si_texture *tex;
933 tex = CALLOC_STRUCT_CL(si_texture);
934 if (!tex)
937 resource = &tex->buffer;
943 tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format));
944 tex->surface = *surface;
949 for (unsigned i = 0; i < ARRAY_SIZE(tex->depth_clear_value); i++)
950 tex->depth_clear_value[i] = 1.0;
958 tex->tc_compatible_htile = (sscreen->info.gfx_level == GFX8 &&
959 tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) ||
962 tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE &&
963 tex->buffer.b.b.last_level > 0);
968 if (tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
970 tex->db_render_format = base->format;
972 tex->db_render_format = PIPE_FORMAT_Z32_FLOAT;
973 tex->upgraded_depth = base->format != PIPE_FORMAT_Z32_FLOAT &&
977 tex->db_render_format = base->format;
981 tex->last_msaa_resolve_target_micro_mode = tex->surface.micro_tile_mode;
983 if (!ac_surface_override_offset_stride(&sscreen->info, &tex->surface,
984 tex->buffer.b.b.last_level + 1,
985 offset, pitch_in_bytes / tex->surface.bpe))
988 if (tex->is_depth) {
989 tex->htile_stencil_disabled = !tex->surface.has_stencil;
992 tex->can_sample_z = true;
993 tex->can_sample_s = true;
998 tex->htile_stencil_disabled = true;
1000 tex->can_sample_z = !tex->surface.u.legacy.depth_adjusted;
1001 tex->can_sample_s = !tex->surface.u.legacy.stencil_adjusted;
1009 tex->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE)
1010 tex->htile_stencil_disabled = false;
1013 tex->db_compatible = surface->flags & RADEON_SURF_ZBUFFER;
1015 if (tex->surface.cmask_offset) {
1017 tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
1018 tex->cmask_buffer = &tex->buffer;
1058 if (tex->cmask_buffer) {
1061 si_init_buffer_clear(&clears[num_clears++], &tex->cmask_buffer->b.b,
1062 tex->surface.cmask_offset, tex->surface.cmask_size,
1065 if (tex->is_depth && tex->surface.meta_offset) {
1068 if (sscreen->info.gfx_level >= GFX9 || tex->tc_compatible_htile)
1072 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset,
1073 tex->surface.meta_size, clear_value);
1077 if (!(surface->flags & RADEON_SURF_IMPORTED) && !tex->is_depth && tex->surface.meta_offset) {
1083 if (tex->surface.num_meta_levels == tex->buffer.b.b.last_level + 1 &&
1084 tex->buffer.b.b.nr_samples <= 2) {
1087 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset,
1088 tex->surface.meta_size, DCC_CLEAR_0000);
1092 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset,
1093 tex->surface.meta_size, DCC_UNCOMPRESSED);
1096 if (tex->buffer.b.b.nr_samples >= 2) {
1099 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset,
1100 tex->surface.meta_size, DCC_UNCOMPRESSED);
1105 for (unsigned i = 0; i < tex->surface.num_meta_levels; i++) {
1106 if (!tex->surface.u.legacy.color.dcc_level[i].dcc_fast_clear_size)
1109 size = tex->surface.u.legacy.color.dcc_level[i].dcc_offset +
1110 tex->surface.u.legacy.color.dcc_level[i].dcc_fast_clear_size;
1116 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset, size,
1120 if (size != tex->surface.meta_size) {
1122 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset + size,
1123 tex->surface.meta_size - size, DCC_UNCOMPRESSED);
1130 if (tex->surface.display_dcc_offset && !(surface->flags & RADEON_SURF_IMPORTED)) {
1134 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.display_dcc_offset,
1135 tex->surface.u.gfx9.color.display_dcc_size,
1147 tex->cmask_base_address_reg = (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8;
1153 tex->buffer.gpu_address, tex->buffer.gpu_address + tex->buffer.buf->size,
1162 si_print_texture_info(sscreen, tex, &log);
1168 return tex;
1171 FREE_CL(tex);
1267 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1317 struct si_texture *tex =
1320 if (!tex) {
1325 tex->plane_index = i;
1326 tex->num_planes = num_planes;
1329 plane0 = last_plane = tex;
1331 last_plane->buffer.b.b.next = &tex->buffer.b.b;
1332 last_plane = tex;
1348 struct si_texture *tex = (struct si_texture *)res;
1349 struct radeon_surf *surface = &tex->surface;
1542 struct si_texture *tex;
1582 tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf,
1584 if (!tex)
1587 tex->buffer.b.is_shared = true;
1588 tex->buffer.external_usage = usage;
1589 tex->num_planes = 1;
1590 if (tex->buffer.flags & RADEON_FLAG_ENCRYPTED)
1591 tex->buffer.b.b.bind |= PIPE_BIND_PROTECTED;
1594 struct pipe_resource *next_plane = tex->buffer.b.b.next;
1598 ++tex->num_planes;
1602 unsigned nplanes = ac_surface_get_nplanes(&tex->surface);
1606 if (plane >= nplanes || ptex->buffer != tex->buffer.buf ||
1608 &tex->surface, plane, 0) ||
1610 &tex->surface, plane, 0)) {
1611 si_texture_reference(&tex, NULL);
1618 if (plane != nplanes && tex->num_planes == 1) {
1619 si_texture_reference(&tex, NULL);
1623 if (!ac_surface_set_umd_metadata(&sscreen->info, &tex->surface,
1624 tex->buffer.b.b.nr_storage_samples,
1625 tex->buffer.b.b.last_level + 1,
1628 si_texture_reference(&tex, NULL);
1632 if (ac_surface_get_plane_offset(sscreen->info.gfx_level, &tex->surface, 0, 0) +
1633 tex->surface.total_size > buf->size ||
1634 buf->alignment_log2 < tex->surface.alignment_log2) {
1635 si_texture_reference(&tex, NULL);
1641 si_displayable_dcc_needs_explicit_flush(tex)) {
1643 if (si_texture_discard_dcc(sscreen, tex)) {
1645 si_set_tex_bo_metadata(sscreen, tex);
1649 assert(tex->surface.tile_swizzle == 0);
1650 return &tex->buffer.b.b;
1673 struct si_auxiliary_texture *tex = CALLOC_STRUCT_CL(si_auxiliary_texture);
1674 if (!tex)
1676 tex->b.b = *templ;
1677 tex->b.b.flags |= SI_RESOURCE_AUX_PLANE;
1678 tex->stride = whandle->stride;
1679 tex->offset = whandle->offset;
1680 tex->buffer = buf;
1681 pipe_reference_init(&tex->b.b.reference, 1);
1682 tex->b.b.screen = screen;
1684 return &tex->b.b;
1693 struct si_texture *tex = (struct si_texture *)texture;
1697 assert(!tex->flushed_depth_texture);
1699 if (!tex->can_sample_z && tex->can_sample_s) {
1720 } else if (!tex->can_sample_s && tex->can_sample_z) {
1741 tex->flushed_depth_texture =
1743 if (!tex->flushed_depth_texture) {
1794 static bool si_can_invalidate_texture(struct si_screen *sscreen, struct si_texture *tex,
1797 return !tex->buffer.b.is_shared && !(tex->surface.flags & RADEON_SURF_IMPORTED) &&
1798 !(transfer_usage & PIPE_MAP_READ) && tex->buffer.b.b.last_level == 0 &&
1799 util_texrange_covers_whole_level(&tex->buffer.b.b, 0, box->x, box->y, box->z, box->width,
1803 static void si_texture_invalidate_storage(struct si_context *sctx, struct si_texture *tex)
1808 assert(!tex->is_depth);
1809 assert(tex->surface.is_linear);
1812 si_alloc_resource(sscreen, &tex->buffer);
1815 tex->cmask_base_address_reg = (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8;
1819 sctx->num_alloc_tex_transfer_bytes += tex->surface.total_size;
1827 struct si_texture *tex = (struct si_texture *)texture;
1832 bool use_staging_texture = tex->buffer.flags & RADEON_FLAG_ENCRYPTED;
1839 if (tex->buffer.b.b.flags & SI_RESOURCE_AUX_PLANE)
1842 if ((tex->buffer.flags & RADEON_FLAG_ENCRYPTED) && usage & PIPE_MAP_READ)
1845 if (tex->is_depth || tex->buffer.flags & RADEON_FLAG_SPARSE) {
1854 box->height >= 4 && p_atomic_inc_return(&tex->num_level0_transfers) == 10) {
1855 bool can_invalidate = si_can_invalidate_texture(sctx->screen, tex, usage, box);
1857 si_reallocate_texture_inplace(sctx, tex, PIPE_BIND_LINEAR, can_invalidate);
1872 if (!tex->surface.is_linear || (tex->buffer.flags & RADEON_FLAG_ENCRYPTED) ||
1873 (tex->buffer.domains & RADEON_DOMAIN_VRAM && sctx->screen->info.has_dedicated_vram &&
1878 tex->buffer.domains & RADEON_DOMAIN_VRAM || tex->buffer.flags & RADEON_FLAG_GTT_WC;
1880 else if (si_cs_is_buffer_referenced(sctx, tex->buffer.buf, RADEON_USAGE_READWRITE) ||
1881 !sctx->ws->buffer_wait(sctx->ws, tex->buffer.buf, 0, RADEON_USAGE_READWRITE)) {
1883 if (si_can_invalidate_texture(sctx->screen, tex, usage, box))
1884 si_texture_invalidate_storage(sctx, tex);
1911 if (tex->is_depth)
1934 offset = si_texture_get_offset(sctx->screen, tex, real_level, box, &trans->b.b.stride,
1936 buf = &tex->buffer;
1963 struct si_texture *tex = (struct si_texture *)texture;
1969 struct si_resource *buf = stransfer->staging ? stransfer->staging : &tex->buffer;
2064 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex, unsigned level,
2067 struct si_texture *stex = (struct si_texture *)tex;
2070 !vi_dcc_formats_compatible((struct si_screen *)tex->screen, tex->format, view_format);
2075 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex,
2078 struct si_texture *stex = (struct si_texture *)tex;
2080 if (vi_dcc_formats_are_incompatible(tex, level, view_format))
2085 static struct pipe_surface *si_create_surface(struct pipe_context *pipe, struct pipe_resource *tex,
2088 unsigned level = templ->u.tex.level;
2089 unsigned width = u_minify(tex->width0, level);
2090 unsigned height = u_minify(tex->height0, level);
2091 unsigned width0 = tex->width0;
2092 unsigned height0 = tex->height0;
2094 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
2095 const struct util_format_description *tex_desc = util_format_description(tex->format);
2104 unsigned nblks_x = util_format_get_nblocksx(tex->format, width);
2105 unsigned nblks_y = util_format_get_nblocksy(tex->format, height);
2110 width0 = util_format_get_nblocksx(tex->format, width0);
2111 height0 = util_format_get_nblocksy(tex->format, height0);
2120 assert(templ->u.tex.first_layer <= util_max_layer(tex, templ->u.tex.level));
2121 assert(templ->u.tex.last_layer <= util_max_layer(tex, templ->u.tex.level));
2124 pipe_resource_reference(&surface->base.texture, tex);
2135 tex->target != PIPE_BUFFER &&
2136 vi_dcc_formats_are_incompatible(tex, templ->u.tex.level, templ->format);
2273 struct si_texture *tex = (struct si_texture *)resource;
2279 if (bind & PIPE_BIND_LINEAR && !tex->surface.is_linear)
2282 if (bind & PIPE_BIND_SCANOUT && !tex->surface.is_displayable)