Lines Matching refs:templ
46 const struct pipe_resource *templ,
432 struct pipe_resource templ = tex->buffer.b.b;
435 templ.bind |= new_bind_flag;
445 if (si_choose_tiling(sctx->screen, &templ, false) != RADEON_SURF_MODE_LINEAR_ALIGNED)
449 new_tex = (struct si_texture *)screen->resource_create(screen, &templ);
455 for (i = 0; i <= templ.last_level; i++) {
458 u_box_3d(0, 0, 0, u_minify(templ.width0, i), u_minify(templ.height0, i),
459 util_num_layers(&templ, i), &box);
472 tex->buffer.b.b.bind = templ.bind;
774 struct pipe_resource templ = res->b.b;
775 templ.bind |= PIPE_BIND_SHARED;
777 struct pipe_resource *newb = screen->resource_create(screen, &templ);
1176 const struct pipe_resource *templ,
1179 const struct util_format_description *desc = util_format_description(templ->format);
1180 bool force_tiling = templ->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING;
1181 bool is_depth_stencil = util_format_is_depth_or_stencil(templ->format) &&
1182 !(templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH);
1185 if (templ->nr_samples > 1)
1189 if (templ->flags & SI_RESOURCE_FLAG_FORCE_LINEAR)
1201 if (!force_tiling && !is_depth_stencil && !util_format_is_compressed(templ->format)) {
1203 (templ->bind & PIPE_BIND_SCANOUT && sscreen->debug_flags & DBG(NO_DISPLAY_TILING)))
1212 if (templ->bind & PIPE_BIND_CURSOR)
1215 if (templ->bind & PIPE_BIND_LINEAR)
1219 if (templ->target == PIPE_TEXTURE_1D || templ->target == PIPE_TEXTURE_1D_ARRAY ||
1222 templ->height0 <= 2)
1226 if (templ->usage == PIPE_USAGE_STAGING || templ->usage == PIPE_USAGE_STREAM)
1231 if (templ->width0 <= 16 || templ->height0 <= 16 || (sscreen->debug_flags & DBG(NO_2D_TILING)))
1240 const struct pipe_resource *templ,
1244 bool is_zs = util_format_is_depth_or_stencil(templ->format);
1246 if (templ->nr_samples >= 2) {
1252 ((struct pipe_resource *)templ)->nr_samples =
1253 ((struct pipe_resource *)templ)->nr_storage_samples = sscreen->eqaa_force_z_samples;
1255 ((struct pipe_resource *)templ)->nr_samples = sscreen->eqaa_force_coverage_samples;
1256 ((struct pipe_resource *)templ)->nr_storage_samples = sscreen->eqaa_force_color_samples;
1260 bool is_flushed_depth = templ->flags & SI_RESOURCE_FLAG_FLUSHED_DEPTH ||
1261 templ->flags & SI_RESOURCE_FLAG_FORCE_LINEAR;
1270 (templ->flags & PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY) &&
1273 enum radeon_surf_mode tile_mode = si_choose_tiling(sscreen, templ, tc_compatible_htile);
1285 unsigned num_planes = util_format_get_num_planes(templ->format);
1290 plane_templ[i] = *templ;
1291 plane_templ[i].format = util_format_get_plane_format(templ->format, i);
1292 plane_templ[i].width0 = util_format_get_plane_width(templ->format, i, templ->width0);
1293 plane_templ[i].height0 = util_format_get_plane_height(templ->format, i, templ->height0);
1340 const struct pipe_resource *templ)
1342 return si_texture_create_with_modifier(screen, templ, DRM_FORMAT_MOD_INVALID);
1474 const struct pipe_resource *templ)
1480 return templ->width0 <= max_width && templ->height0 <= max_height;
1485 const struct pipe_resource *templ,
1490 assert(templ->target != PIPE_BUFFER);
1494 si_query_dmabuf_modifiers(screen, templ->format, 0, NULL, NULL, &allowed_mod_count);
1502 si_query_dmabuf_modifiers(screen, templ->format, allowed_mod_count, allowed_modifiers, NULL, &allowed_mod_count);
1512 if (modifiers[j] == allowed_modifiers[i] && si_modifier_supports_resource(screen, modifiers[j], templ))
1526 return si_texture_create_with_modifier(screen, templ, modifier);
1535 const struct pipe_resource *templ,
1577 r = si_init_surface(sscreen, &surface, templ, metadata.mode, modifier, true,
1582 tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf,
1654 const struct pipe_resource *templ,
1661 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT &&
1662 templ->target != PIPE_TEXTURE_2D_ARRAY) ||
1663 templ->last_level != 0)
1668 templ->bind & PIPE_BIND_PRIME_BLIT_DST);
1676 tex->b.b = *templ;
1687 return si_texture_from_winsys_buffer(sscreen, templ, buf, whandle->stride, whandle->offset,
2086 const struct pipe_surface *templ)
2088 unsigned level = templ->u.tex.level;
2094 if (tex->target != PIPE_BUFFER && templ->format != tex->format) {
2096 const struct util_format_description *templ_desc = util_format_description(templ->format);
2120 assert(templ->u.tex.first_layer <= util_max_layer(tex, templ->u.tex.level));
2121 assert(templ->u.tex.last_layer <= util_max_layer(tex, templ->u.tex.level));
2126 surface->base.format = templ->format;
2129 surface->base.u = templ->u;
2136 vi_dcc_formats_are_incompatible(tex, templ->u.tex.level, templ->format);
2242 const struct pipe_resource *templ,
2250 if (templ->target == PIPE_BUFFER)
2251 res = si_buffer_from_winsys_buffer(screen, templ, memobj->buf, offset);
2253 res = si_texture_from_winsys_buffer(sscreen, templ, memobj->buf,