Lines Matching refs:sscreen
45 static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen,
131 static unsigned si_texture_get_offset(struct si_screen *sscreen, struct si_texture *tex,
135 if (sscreen->info.gfx_level >= GFX9) {
173 static int si_init_surface(struct si_screen *sscreen, struct radeon_surf *surface,
197 if ((sscreen->debug_flags & DBG(NO_HYPERZ)) ||
201 (sscreen->info.gfx_level >= GFX9 || array_mode == RADEON_SURF_MODE_2D)) {
207 if (sscreen->info.gfx_level == GFX8)
218 if (sscreen->info.gfx_level >= GFX8 && modifier == DRM_FORMAT_MOD_INVALID && !is_imported) {
223 if (ptex->nr_samples >= 2 && sscreen->debug_flags & DBG(NO_DCC_MSAA))
230 (sscreen->debug_flags & DBG(NO_DCC) ||
231 (ptex->bind & PIPE_BIND_SCANOUT && sscreen->debug_flags & DBG(NO_DISPLAY_DCC))))
235 if (sscreen->info.gfx_level < GFX10_3 &&
239 switch (sscreen->info.gfx_level) {
242 if (sscreen->info.family == CHIP_STONEY && bpe == 16 && ptex->nr_samples >= 2)
256 if (sscreen->info.family == CHIP_RAVEN && ptex->nr_storage_samples >= 2 && bpe < 4)
262 if (ptex->nr_storage_samples >= 2 && !sscreen->options.dcc_msaa)
286 if (sscreen->debug_flags & DBG(NO_FMASK))
289 if (sscreen->info.gfx_level == GFX9 && (ptex->flags & SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE)) {
298 assert(sscreen->info.gfx_level <= GFX10_3);
302 if (sscreen->info.gfx_level >= GFX10)
316 r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe, array_mode, surface);
343 void si_texture_discard_cmask(struct si_screen *sscreen, struct si_texture *tex)
362 p_atomic_inc(&sscreen->dirty_tex_counter);
363 p_atomic_inc(&sscreen->compressed_colortex_counter);
376 static bool si_texture_discard_dcc(struct si_screen *sscreen, struct si_texture *tex)
385 p_atomic_inc(&sscreen->dirty_tex_counter);
407 * \param sctx the current context if you have one, or sscreen->aux_context
412 struct si_screen *sscreen = sctx->screen;
415 return si_texture_discard_dcc(sscreen, tex);
424 return si_texture_discard_dcc(sscreen, tex);
530 static void si_set_tex_bo_metadata(struct si_screen *sscreen, struct si_texture *tex)
544 sscreen->make_texture_descriptor(sscreen, tex, true, res->target, res->format, swizzle, 0,
547 si_set_mutable_tex_desc_fields(sscreen, tex, &tex->surface.u.legacy.level[0], 0, 0,
550 ac_surface_get_umd_metadata(&sscreen->info, &tex->surface,
553 sscreen->ws->buffer_set_metadata(sscreen->ws, tex->buffer.buf, &md, &tex->surface);
558 struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen;
560 if (sscreen->info.gfx_level <= GFX8)
582 struct si_screen *sscreen = (struct si_screen *)screen;
600 *value = ac_surface_get_plane_stride(sscreen->info.gfx_level,
609 *value = ac_surface_get_plane_offset(sscreen->info.gfx_level,
661 struct si_screen *sscreen = (struct si_screen *)screen;
671 sctx = ctx ? (struct si_context *)ctx : si_get_aux_context(sscreen);
690 si_put_aux_context_flush(sscreen);
698 si_put_aux_context_flush(sscreen);
699 whandle->offset = ac_surface_get_plane_offset(sscreen->info.gfx_level,
701 whandle->stride = ac_surface_get_plane_stride(sscreen->info.gfx_level,
704 return sscreen->ws->buffer_get_handle(sscreen->ws, res->buf, whandle);
708 if (sscreen->ws->buffer_is_suballocated(res->buf) || tex->surface.tile_swizzle ||
710 sscreen->info.has_local_buffers)) {
724 if (sscreen->debug_flags & DBG(NO_EXPORTED_DCC) ||
748 si_texture_discard_cmask(sscreen, tex);
753 si_set_tex_bo_metadata(sscreen, tex);
755 if (sscreen->info.gfx_level >= GFX9) {
767 if (sscreen->ws->buffer_is_suballocated(res->buf) ||
770 sscreen->info.has_local_buffers)) {
780 si_put_aux_context_flush(sscreen);
818 si_put_aux_context_flush(sscreen);
824 return sscreen->ws->buffer_get_handle(sscreen->ws, res->buf, whandle);
827 void si_print_texture_info(struct si_screen *sscreen, struct si_texture *tex,
852 ac_surface_print_info(f, &sscreen->info, &tex->surface);
857 if (sscreen->info.gfx_level >= GFX9) {
923 struct si_screen *sscreen = (struct si_screen *)screen;
925 if (!sscreen->info.has_3d_cube_border_color_mipmap &&
958 tex->tc_compatible_htile = (sscreen->info.gfx_level == GFX8 &&
961 (sscreen->info.gfx_level >= GFX8 &&
969 if (sscreen->info.gfx_level >= GFX9 && base->format == PIPE_FORMAT_Z16_UNORM)
983 if (!ac_surface_override_offset_stride(&sscreen->info, &tex->surface,
991 if (sscreen->info.gfx_level >= GFX9) {
997 if (sscreen->info.gfx_level == GFX10 && base->last_level > 0)
1008 if (sscreen->info.gfx_level == GFX8 &&
1016 assert(sscreen->info.gfx_level < GFX11);
1030 radeon_bo_reference(sscreen->ws, &resource->buf, plane0->buffer.buf);
1039 si_init_resource_fields(sscreen, resource, alloc_size, alignment);
1041 if (!si_alloc_resource(sscreen, resource))
1045 resource->gpu_address = sscreen->ws->buffer_get_virtual_address(resource->buf);
1048 resource->domains = sscreen->ws->buffer_get_initial_domain(resource->buf);
1050 if (sscreen->ws->buffer_get_flags)
1051 resource->flags = sscreen->ws->buffer_get_flags(resource->buf);
1068 if (sscreen->info.gfx_level >= GFX9 || tex->tc_compatible_htile)
1089 } else if (sscreen->info.gfx_level >= GFX9) {
1136 sscreen->info.gfx_level >= GFX11 ? GFX11_DCC_CLEAR_1111_UNORM
1142 si_execute_clears(si_get_aux_context(sscreen), clears, num_clears, 0);
1143 si_put_aux_context_flush(sscreen);
1149 if (sscreen->debug_flags & DBG(VM)) {
1158 if (sscreen->debug_flags & DBG(TEX)) {
1162 si_print_texture_info(sscreen, tex, &log);
1175 static enum radeon_surf_mode si_choose_tiling(struct si_screen *sscreen,
1195 if (sscreen->info.gfx_level == GFX8 && tc_compatible_htile)
1202 if (sscreen->debug_flags & DBG(NO_TILING) ||
1203 (templ->bind & PIPE_BIND_SCANOUT && sscreen->debug_flags & DBG(NO_DISPLAY_TILING)))
1231 if (templ->width0 <= 16 || templ->height0 <= 16 || (sscreen->debug_flags & DBG(NO_2D_TILING)))
1243 struct si_screen *sscreen = (struct si_screen *)screen;
1251 if (is_zs && sscreen->eqaa_force_z_samples) {
1253 ((struct pipe_resource *)templ)->nr_storage_samples = sscreen->eqaa_force_z_samples;
1254 } else if (!is_zs && sscreen->eqaa_force_color_samples) {
1255 ((struct pipe_resource *)templ)->nr_samples = sscreen->eqaa_force_coverage_samples;
1256 ((struct pipe_resource *)templ)->nr_storage_samples = sscreen->eqaa_force_color_samples;
1263 sscreen->info.gfx_level >= GFX8 &&
1269 sscreen->info.family != CHIP_TONGA && sscreen->info.family != CHIP_ICELAND &&
1271 !(sscreen->debug_flags & DBG(NO_HYPERZ)) && !is_flushed_depth &&
1273 enum radeon_surf_mode tile_mode = si_choose_tiling(sscreen, templ, tc_compatible_htile);
1302 if (si_init_surface(sscreen, &surface[i], &plane_templ[i], tile_mode, modifier,
1396 struct si_screen *sscreen = (struct si_screen *)screen;
1399 ac_get_supported_modifiers(&sscreen->info, &(struct ac_modifier_options) {
1400 .dcc = !(sscreen->debug_flags & DBG(NO_DCC)),
1404 .dcc_retile = !(sscreen->debug_flags & DBG(NO_DCC)),
1476 struct si_screen *sscreen = (struct si_screen *)screen;
1479 ac_modifier_max_extent(&sscreen->info, modifier, &max_width, &max_height);
1534 static struct pipe_resource *si_texture_from_winsys_buffer(struct si_screen *sscreen,
1550 sscreen->ws->buffer_get_metadata(sscreen->ws, buf, &metadata, &surface);
1577 r = si_init_surface(sscreen, &surface, templ, metadata.mode, modifier, true,
1582 tex = si_texture_create_object(&sscreen->b, templ, &surface, NULL, buf,
1607 ptex->offset != ac_surface_get_plane_offset(sscreen->info.gfx_level,
1609 ptex->stride != ac_surface_get_plane_stride(sscreen->info.gfx_level,
1623 if (!ac_surface_set_umd_metadata(&sscreen->info, &tex->surface,
1632 if (ac_surface_get_plane_offset(sscreen->info.gfx_level, &tex->surface, 0, 0) +
1643 if (si_texture_discard_dcc(sscreen, tex)) {
1645 si_set_tex_bo_metadata(sscreen, tex);
1657 struct si_screen *sscreen = (struct si_screen *)screen;
1666 buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle,
1667 sscreen->info.max_alignment,
1687 return si_texture_from_winsys_buffer(sscreen, templ, buf, whandle->stride, whandle->offset,
1794 static bool si_can_invalidate_texture(struct si_screen *sscreen, struct si_texture *tex,
1805 struct si_screen *sscreen = sctx->screen;
1812 si_alloc_resource(sscreen, &tex->buffer);
1817 p_atomic_inc(&sscreen->dirty_tex_counter);
2006 bool vi_dcc_formats_compatible(struct si_screen *sscreen, enum pipe_format format1,
2012 if (sscreen->info.gfx_level >= GFX11)
2050 if (vi_alpha_is_on_msb(sscreen, format1) != vi_alpha_is_on_msb(sscreen, format2))
2213 struct si_screen *sscreen = (struct si_screen *)screen;
2220 buf = sscreen->ws->buffer_from_handle(sscreen->ws, whandle, sscreen->info.max_alignment, false);
2246 struct si_screen *sscreen = (struct si_screen *)screen;
2253 res = si_texture_from_winsys_buffer(sscreen, templ, memobj->buf,
2266 radeon_bo_reference(sscreen->ws, &buf, memobj->buf);
2296 struct si_screen *sscreen = (struct si_screen *)screen;
2344 if (multi_sample && sscreen->info.gfx_level != GFX9)
2370 void si_init_screen_texture_functions(struct si_screen *sscreen)
2372 sscreen->b.resource_from_handle = si_texture_from_handle;
2373 sscreen->b.resource_get_handle = si_texture_get_handle;
2374 sscreen->b.resource_get_param = si_resource_get_param;
2375 sscreen->b.resource_get_info = si_texture_get_info;
2376 sscreen->b.resource_from_memobj = si_resource_from_memobj;
2377 sscreen->b.memobj_create_from_handle = si_memobj_from_handle;
2378 sscreen->b.memobj_destroy = si_memobj_destroy;
2379 sscreen->b.check_resource_capability = si_check_resource_capability;
2380 sscreen->b.get_sparse_texture_virtual_page_size =
2387 if (sscreen->info.gfx_level >= GFX9 && sscreen->info.kernel_has_modifiers) {
2388 sscreen->b.resource_create_with_modifiers = si_texture_create_with_modifiers;
2389 sscreen->b.query_dmabuf_modifiers = si_query_dmabuf_modifiers;
2390 sscreen->b.is_dmabuf_modifier_supported = si_is_dmabuf_modifier_supported;
2391 sscreen->b.get_dmabuf_modifier_planes = si_get_dmabuf_modifier_planes;