Lines Matching refs:buffer
330 ctx->flush_resource(ctx, &tex->buffer.b.b);
348 assert(tex->buffer.b.b.nr_samples <= 1);
351 tex->cmask_base_address_reg = tex->buffer.gpu_address >> 8;
356 if (tex->cmask_buffer != &tex->buffer)
371 (!tex->buffer.b.is_shared ||
372 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE)) &&
432 struct pipe_resource templ = tex->buffer.b.b;
437 if (tex->buffer.b.is_shared || tex->num_planes > 1)
461 si_resource_copy_region(&sctx->b, &new_tex->buffer.b.b,
462 i, 0, 0, 0, &tex->buffer.b.b, i, &box);
472 tex->buffer.b.b.bind = templ.bind;
473 radeon_bo_reference(sctx->screen->ws, &tex->buffer.buf, new_tex->buffer.buf);
474 tex->buffer.gpu_address = new_tex->buffer.gpu_address;
475 tex->buffer.memory_usage_kb = new_tex->buffer.memory_usage_kb;
476 tex->buffer.bo_size = new_tex->buffer.bo_size;
477 tex->buffer.bo_alignment_log2 = new_tex->buffer.bo_alignment_log2;
478 tex->buffer.domains = new_tex->buffer.domains;
479 tex->buffer.flags = new_tex->buffer.flags;
488 if (tex->cmask_buffer == &tex->buffer)
493 if (new_tex->cmask_buffer == &new_tex->buffer)
494 tex->cmask_buffer = &tex->buffer;
532 struct pipe_resource *res = &tex->buffer.b.b;
551 tex->buffer.b.b.last_level + 1,
553 sscreen->ws->buffer_set_metadata(sscreen->ws, tex->buffer.buf, &md, &tex->surface);
558 struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen;
694 whandle->size = tex->buffer.bo_size;
709 (tex->buffer.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
766 /* Move a suballocated buffer into a non-suballocated allocation. */
769 (tex->buffer.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
773 /* Allocate a new buffer with PIPE_BIND_SHARED. */
784 /* Copy the old buffer contents to the new one. */
789 /* Move the new buffer storage to the old pipe_resource. */
839 tex->buffer.b.b.width0, tex->buffer.b.b.height0,
840 tex->buffer.b.b.depth0, tex->buffer.b.b.array_size,
841 tex->buffer.b.b.last_level, tex->buffer.b.b.nr_samples);
847 util_format_short_name(tex->buffer.b.b.format));
862 for (i = 0; i <= tex->buffer.b.b.last_level; i++)
870 for (i = 0; i <= tex->buffer.b.b.last_level; i++)
877 u_minify(tex->buffer.b.b.width0, i), u_minify(tex->buffer.b.b.height0, i),
878 u_minify(tex->buffer.b.b.depth0, i), tex->surface.u.legacy.level[i].nblk_x,
883 for (i = 0; i <= tex->buffer.b.b.last_level; i++) {
891 u_minify(tex->buffer.b.b.width0, i), u_minify(tex->buffer.b.b.height0, i),
892 u_minify(tex->buffer.b.b.depth0, i),
937 resource = &tex->buffer;
943 tex->is_depth = util_format_has_depth(util_format_description(tex->buffer.b.b.format));
963 tex->buffer.b.b.last_level > 0);
984 tex->buffer.b.b.last_level + 1,
1018 tex->cmask_buffer = &tex->buffer;
1023 /* The buffer is shared with the first plane. */
1024 resource->bo_size = plane0->buffer.bo_size;
1025 resource->bo_alignment_log2 = plane0->buffer.bo_alignment_log2;
1026 resource->flags = plane0->buffer.flags;
1027 resource->domains = plane0->buffer.domains;
1028 resource->memory_usage_kb = plane0->buffer.memory_usage_kb;
1030 radeon_bo_reference(sscreen->ws, &resource->buf, plane0->buffer.buf);
1031 resource->gpu_address = plane0->buffer.gpu_address;
1038 /* Create the backing buffer. */
1072 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset,
1083 if (tex->surface.num_meta_levels == tex->buffer.b.b.last_level + 1 &&
1084 tex->buffer.b.b.nr_samples <= 2) {
1087 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset,
1092 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset,
1096 if (tex->buffer.b.b.nr_samples >= 2) {
1099 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset,
1116 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset, size,
1122 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.meta_offset + size,
1134 si_init_buffer_clear(&clears[num_clears++], &tex->buffer.b.b, tex->surface.display_dcc_offset,
1147 tex->cmask_base_address_reg = (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8;
1153 tex->buffer.gpu_address, tex->buffer.gpu_address + tex->buffer.buf->size,
1275 /* This allocates textures with multiple planes like NV12 in 1 buffer. */
1331 last_plane->buffer.b.b.next = &tex->buffer.b.b;
1587 tex->buffer.b.is_shared = true;
1588 tex->buffer.external_usage = usage;
1590 if (tex->buffer.flags & RADEON_FLAG_ENCRYPTED)
1591 tex->buffer.b.b.bind |= PIPE_BIND_PROTECTED;
1594 struct pipe_resource *next_plane = tex->buffer.b.b.next;
1606 if (plane >= nplanes || ptex->buffer != tex->buffer.buf ||
1624 tex->buffer.b.b.nr_storage_samples,
1625 tex->buffer.b.b.last_level + 1,
1650 return &tex->buffer.b.b;
1680 tex->buffer = buf;
1797 return !tex->buffer.b.is_shared && !(tex->surface.flags & RADEON_SURF_IMPORTED) &&
1798 !(transfer_usage & PIPE_MAP_READ) && tex->buffer.b.b.last_level == 0 &&
1799 util_texrange_covers_whole_level(&tex->buffer.b.b, 0, box->x, box->y, box->z, box->width,
1811 /* Reallocate the buffer in the same pipe_resource. */
1812 si_alloc_resource(sscreen, &tex->buffer);
1815 tex->cmask_base_address_reg = (tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8;
1832 bool use_staging_texture = tex->buffer.flags & RADEON_FLAG_ENCRYPTED;
1839 if (tex->buffer.b.b.flags & SI_RESOURCE_AUX_PLANE)
1842 if ((tex->buffer.flags & RADEON_FLAG_ENCRYPTED) && usage & PIPE_MAP_READ)
1845 if (tex->is_depth || tex->buffer.flags & RADEON_FLAG_SPARSE) {
1872 if (!tex->surface.is_linear || (tex->buffer.flags & RADEON_FLAG_ENCRYPTED) ||
1873 (tex->buffer.domains & RADEON_DOMAIN_VRAM && sctx->screen->info.has_dedicated_vram &&
1878 tex->buffer.domains & RADEON_DOMAIN_VRAM || tex->buffer.flags & RADEON_FLAG_GTT_WC;
1880 else if (si_cs_is_buffer_referenced(sctx, tex->buffer.buf, RADEON_USAGE_READWRITE) ||
1881 !sctx->ws->buffer_wait(sctx->ws, tex->buffer.buf, 0, RADEON_USAGE_READWRITE)) {
1920 trans->staging = &staging->buffer;
1936 buf = &tex->buffer;
1969 struct si_resource *buf = stransfer->staging ? stransfer->staging : &tex->buffer;
1990 * usage will be slightly higher than given here because of the buffer