Lines Matching defs:ptex
174 const struct pipe_resource *ptex, enum radeon_surf_mode array_mode,
178 const struct util_format_description *desc = util_format_description(ptex->format);
187 if (!is_flushed_depth && ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
190 bpe = util_format_get_blocksize(ptex->format);
198 (ptex->bind & PIPE_BIND_SHARED) || is_imported) {
220 if (ptex->flags & SI_RESOURCE_FLAG_DISABLE_DCC)
223 if (ptex->nr_samples >= 2 && sscreen->debug_flags & DBG(NO_DCC_MSAA))
231 (ptex->bind & PIPE_BIND_SCANOUT && sscreen->debug_flags & DBG(NO_DISPLAY_DCC))))
236 ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT)
242 if (sscreen->info.family == CHIP_STONEY && bpe == 16 && ptex->nr_samples >= 2)
246 if (ptex->nr_storage_samples >= 4 && ptex->array_size > 1)
256 if (sscreen->info.family == CHIP_RAVEN && ptex->nr_storage_samples >= 2 && bpe < 4)
262 if (ptex->nr_storage_samples >= 2 && !sscreen->options.dcc_msaa)
276 assert(ptex->nr_samples <= 1 && ptex->array_size == 1 && ptex->depth0 == 1 &&
277 ptex->last_level == 0 && !(flags & RADEON_SURF_Z_OR_SBUFFER));
282 if (ptex->bind & PIPE_BIND_SHARED)
289 if (sscreen->info.gfx_level == GFX9 && (ptex->flags & SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE)) {
291 surface->micro_tile_mode = SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex->flags);
294 if (ptex->flags & SI_RESOURCE_FLAG_FORCE_MSAA_TILING) {
306 if (ptex->flags & PIPE_RESOURCE_FLAG_SPARSE) {
316 r = sscreen->ws->surface_init(sscreen->ws, ptex, flags, bpe, array_mode, surface);
1605 struct si_auxiliary_texture *ptex = (struct si_auxiliary_texture *)next_plane;
1606 if (plane >= nplanes || ptex->buffer != tex->buffer.buf ||
1607 ptex->offset != ac_surface_get_plane_offset(sscreen->info.gfx_level,
1609 ptex->stride != ac_surface_get_plane_stride(sscreen->info.gfx_level,