Lines Matching refs:state
66 * Inferred framebuffer and blender state.
138 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
139 struct si_surface *surf = (struct si_surface *)sctx->framebuffer.state.cbufs[i];
440 const struct pipe_blend_state *state, unsigned mode)
447 bool logicop_enable = state->logicop_enable && state->logicop_func != PIPE_LOGICOP_COPY;
452 blend->alpha_to_coverage = state->alpha_to_coverage;
453 blend->alpha_to_one = state->alpha_to_one;
454 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
457 state->rt[0].rgb_func == PIPE_BLEND_ADD &&
458 state->rt[0].alpha_func == PIPE_BLEND_ADD &&
459 state->rt[0].rgb_src_factor == PIPE_BLENDFACTOR_DST_COLOR &&
460 state->rt[0].alpha_src_factor == PIPE_BLENDFACTOR_DST_COLOR &&
461 state->rt[0].rgb_dst_factor == PIPE_BLENDFACTOR_ZERO &&
462 state->rt[0].alpha_dst_factor == PIPE_BLENDFACTOR_ZERO &&
465 unsigned num_shader_outputs = state->max_rt + 1; /* estimate */
470 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
475 if (state->alpha_to_coverage && state->alpha_to_coverage_dither) {
477 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
483 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
489 if (state->alpha_to_coverage)
498 /* state->rt entries > 0 only written if independent blending */
499 const int j = state->independent_blend_enable ? i : 0;
501 unsigned eqRGB = state->rt[j].rgb_func;
502 unsigned srcRGB = state->rt[j].rgb_src_factor;
503 unsigned dstRGB = state->rt[j].rgb_dst_factor;
504 unsigned eqA = state->rt[j].alpha_func;
505 unsigned srcA = state->rt[j].alpha_src_factor;
506 unsigned dstA = state->rt[j].alpha_dst_factor;
538 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
539 if (state->rt[j].colormask)
542 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
587 /* Set blend state. */
647 static void *si_create_blend_state(struct pipe_context *ctx, const struct pipe_blend_state *state)
649 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
654 if (sctx->framebuffer.state.nr_cbufs == 1) {
715 struct pipe_vertex_state *state,
725 sctx->real_draw_vertex_state(ctx, state, partial_velem_mask, info, draws, num_draws);
728 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
732 struct si_state_blend *blend = (struct si_state_blend *)state;
784 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
788 if (sctx->queued.named.blend == state)
791 si_pm4_free_state(sctx, (struct si_pm4_state*)state, SI_STATE_IDX(blend));
794 static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend_color *state)
799 sctx->blend_color = *state;
800 sctx->blend_color_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
818 static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_state *state)
824 if (memcmp(&sctx->clip_state, state, sizeof(*state)) == 0)
827 sctx->clip_state = *state;
828 sctx->clip_state_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
832 cb.user_buffer = state->ucp;
883 * inferred state between framebuffer and rasterizer
889 if (!rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
897 switch (sctx->framebuffer.state.zsbuf->texture->format) {
930 static void *si_create_rs_state(struct pipe_context *ctx, const struct pipe_rasterizer_state *state)
942 rs->scissor_enable = state->scissor;
943 rs->clip_halfz = state->clip_halfz;
944 rs->two_side = state->light_twoside;
945 rs->multisample_enable = state->multisample;
946 rs->force_persample_interp = state->force_persample_interp;
947 rs->clip_plane_enable = state->clip_plane_enable;
948 rs->half_pixel_center = state->half_pixel_center;
949 rs->line_stipple_enable = state->line_stipple_enable;
950 rs->poly_stipple_enable = state->poly_stipple_enable;
951 rs->line_smooth = state->line_smooth;
952 rs->line_width = state->line_width;
953 rs->poly_smooth = state->poly_smooth;
954 rs->point_smooth = state->point_smooth;
955 rs->uses_poly_offset = state->offset_point || state->offset_line || state->offset_tri;
956 rs->clamp_fragment_color = state->clamp_fragment_color;
957 rs->clamp_vertex_color = state->clamp_vertex_color;
958 rs->flatshade = state->flatshade;
959 rs->flatshade_first = state->flatshade_first;
960 rs->sprite_coord_enable = state->sprite_coord_enable;
961 rs->rasterizer_discard = state->rasterizer_discard;
963 (state->fill_front == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_FRONT)) ||
964 (state->fill_back == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_BACK));
966 (state->fill_front == PIPE_POLYGON_MODE_POINT && !(state->cull_face & PIPE_FACE_FRONT)) ||
967 (state->fill_back == PIPE_POLYGON_MODE_POINT && !(state->cull_face & PIPE_FACE_BACK));
968 rs->pa_sc_line_stipple = state->line_stipple_enable
969 ? S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
970 S_028A0C_REPEAT_COUNT(state->line_stipple_factor)
974 rs->perpendicular_end_caps = state->multisample &&
975 state->line_width > 2 && !state->line_stipple_enable;
977 rs->pa_cl_clip_cntl = S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
978 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
979 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
980 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
984 SI_NGG_CULL_CLIP_PLANE_ENABLE(state->clip_plane_enable);
989 SI_NGG_CULL_CLIP_PLANE_ENABLE(state->clip_plane_enable);
998 if (!state->front_ccw) {
999 cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
1000 cull_back = !!(state->cull_face & PIPE_FACE_BACK);
1002 cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
1003 cull_front = !!(state->cull_face & PIPE_FACE_BACK);
1019 S_0286D4_FLAT_SHADE_ENA(1) | S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
1024 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
1027 tmp = (unsigned)(state->point_size * 8.0);
1030 if (state->point_size_per_vertex) {
1031 psize_min = util_get_min_point_size(state);
1035 psize_min = state->point_size;
1036 psize_max = state->point_size;
1046 S_028A08_WIDTH(si_pack_float_12p4(state->line_width / 2)));
1049 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
1050 S_028A48_MSAA_ENABLE(state->multisample || state->poly_smooth || state->line_smooth) |
1055 (state->fill_front != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_FRONT)) ||
1056 (state->fill_back != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_BACK));
1059 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
1060 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1061 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1062 S_028814_FACE(!state->front_ccw) |
1063 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
1064 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
1065 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
1067 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1068 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)) |
1074 if (state->bottom_edge_rule) {
1108 float offset_units = state->offset_units;
1109 float offset_scale = state->offset_scale * 16.0f;
1112 if (!state->offset_units_unscaled) {
1131 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
1141 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1145 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1158 /* NGG cull state uses multisample_enable. */
1220 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1223 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1225 if (sctx->queued.named.rasterizer == state)
1233 * inferred state between dsa and stencil ref
1238 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1254 static void si_set_stencil_ref(struct pipe_context *ctx, const struct pipe_stencil_ref state)
1258 if (memcmp(&sctx->stencil_ref.state, &state, sizeof(state)) == 0)
1261 sctx->stencil_ref.state = state;
1304 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1307 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1309 return !state->enabled || !state->writemask ||
1311 (state->func == PIPE_FUNC_ALWAYS && si_order_invariant_stencil_op(state->zpass_op) &&
1312 si_order_invariant_stencil_op(state->zfail_op)) ||
1313 (state->func == PIPE_FUNC_NEVER && si_order_invariant_stencil_op(state->fail_op));
1317 const struct pipe_depth_stencil_alpha_state *state)
1328 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1329 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1330 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1331 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1334 S_028800_Z_ENABLE(state->depth_enabled) | S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
1335 S_028800_ZFUNC(state->depth_func) | S_028800_DEPTH_BOUNDS_ENABLE(state->depth_bounds_test);
1338 if (state->stencil[0].enabled) {
1340 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1342 S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1344 S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1346 S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1348 if (state->stencil[1].enabled) {
1350 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1352 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1354 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1356 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1361 if (state->alpha_enabled) {
1362 dsa->alpha_func = state->alpha_func;
1365 fui(state->alpha_ref_value));
1371 if (state->stencil[0].enabled)
1373 if (state->depth_bounds_test) {
1374 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth_bounds_min));
1375 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth_bounds_max));
1378 dsa->depth_enabled = state->depth_enabled;
1379 dsa->depth_write_enabled = state->depth_enabled && state->depth_writemask;
1380 dsa->stencil_enabled = state->stencil[0].enabled;
1382 (util_writes_stencil(&state->stencil[0]) || util_writes_stencil(&state->stencil[1]));
1386 state->depth_func == PIPE_FUNC_NEVER || state->depth_func == PIPE_FUNC_LESS ||
1387 state->depth_func == PIPE_FUNC_LEQUAL || state->depth_func == PIPE_FUNC_GREATER ||
1388 state->depth_func == PIPE_FUNC_GEQUAL;
1392 (!dsa->depth_write_enabled && si_order_invariant_stencil_state(&state->stencil[0]) &&
1393 si_order_invariant_stencil_state(&state->stencil[1]));
1402 (state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER));
1405 (state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER);
1410 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1414 struct si_state_dsa *dsa = state;
1444 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1448 if (sctx->queued.named.dsa == state)
1451 si_pm4_free_state(sctx, (struct si_pm4_state*)state, SI_STATE_IDX(dsa));
2853 if (sctx->framebuffer.state.zsbuf) {
2854 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2868 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2878 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2880 for (int i = 0; i < state->nr_cbufs; ++i) {
2884 if (!state->cbufs[i])
2886 surf = (struct si_surface *)state->cbufs[i];
2911 const struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2913 for (unsigned i = 0; i < state->nr_cbufs; i++) {
2914 if (state->cbufs[i])
2915 si_mark_display_dcc_dirty(sctx, (struct si_texture *)state->cbufs[i]->texture);
2920 const struct pipe_framebuffer_state *state)
2928 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2931 ((struct si_texture *)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2938 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2946 for (i = 0; i < state->nr_cbufs; i++) {
2947 if (!state->cbufs[i])
2950 surf = (struct si_surface *)state->cbufs[i];
2963 /* Only flush TC when changing the framebuffer state, because
3013 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
3014 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
3016 si_dec_framebuffer_counters(&sctx->framebuffer.state);
3017 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
3029 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
3039 for (i = 0; i < state->nr_cbufs; i++) {
3040 if (!state->cbufs[i])
3043 surf = (struct si_surface *)state->cbufs[i];
3102 if (state->zsbuf) {
3103 surf = (struct si_surface *)state->zsbuf;
3126 /* NGG cull state uses the sample count. */
3138 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3193 /* Prevent textures decompression when the framebuffer state
3203 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3204 unsigned i, nr_cbufs = state->nr_cbufs;
3219 cb = (struct si_surface *)state->cbufs[i];
3271 bool is_msaa_resolve_dst = state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 &&
3272 state->cbufs[1] == &cb->base &&
3273 state->cbufs[1]->texture->nr_samples <= 1;
3462 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3463 struct si_surface *zb = (struct si_surface *)state->zsbuf;
3605 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3699 if (sctx->framebuffer.state.zsbuf) {
3700 struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
3831 if (sctx->framebuffer.state.zsbuf) {
3832 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3898 * @param state 256-bit descriptor; only the high 128 bits are filled in
3902 uint32_t *state)
3940 state[4] = 0;
3941 state[5] = S_008F04_STRIDE(stride);
3942 state[6] = num_records;
3943 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3958 state[7] |= S_008F0C_FORMAT(fmt->img_format) |
3969 state[7] |= S_008F0C_NUM_FORMAT(num_format) | S_008F0C_DATA_FORMAT(data_format);
4009 unsigned depth, uint32_t *state, uint32_t *fmask_state)
4079 state[0] = 0;
4080 state[1] = S_00A004_FORMAT(img_format) | S_00A004_WIDTH_LO(width - 1);
4081 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) | S_00A008_HEIGHT(height - 1) |
4084 state[3] =
4095 state[4] =
4098 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
4105 state[1] |= S_00A004_MAX_MIP(max_mip);
4107 state[5] |= S_00A014_MAX_MIP(max_mip);
4109 state[6] = 0;
4110 state[7] = 0;
4113 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
4195 unsigned depth, uint32_t *state, uint32_t *fmask_state)
4338 state[0] = 0;
4339 state[1] = (S_008F14_DATA_FORMAT(data_format) | S_008F14_NUM_FORMAT(num_format));
4340 state[2] = (S_008F18_WIDTH(width - 1) | S_008F18_HEIGHT(height - 1) | S_008F18_PERF_MOD(4));
4341 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4348 state[4] = 0;
4349 state[5] = S_008F24_BASE_ARRAY(first_layer);
4350 state[6] = 0;
4351 state[7] = 0;
4360 state[4] |= S_008F20_DEPTH(depth - 1);
4362 state[4] |= S_008F20_DEPTH(last_layer);
4364 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
4365 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ? util_logbase2(num_samples)
4368 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
4369 state[4] |= S_008F20_DEPTH(depth - 1);
4370 state[5] |= S_008F24_LAST_ARRAY(last_layer);
4374 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4377 * bits in the first dword of sampler state.
4381 state[7] = C_008F30_MAX_ANISO_RATIO;
4383 state[7] = 0xffffffff;
4520 * @param state sampler view template
4524 const struct pipe_sampler_view *state)
4530 unsigned last_layer = state->u.tex.last_layer;
4538 view->base = *state;
4546 if (state->format == PIPE_FORMAT_X24S8_UINT || state->format == PIPE_FORMAT_S8X24_UINT ||
4547 state->format == PIPE_FORMAT_X32_S8X24_UINT || state->format == PIPE_FORMAT_S8_UINT)
4553 state->format, state->u.buf.size);
4555 si_make_buffer_descriptor(sctx->screen, si_resource(texture), state->format,
4556 state->u.buf.offset, elements, view->state);
4560 state_swizzle[0] = state->swizzle_r;
4561 state_swizzle[1] = state->swizzle_g;
4562 state_swizzle[2] = state->swizzle_b;
4563 state_swizzle[3] = state->swizzle_a;
4566 if (state->target == PIPE_TEXTURE_1D || state->target == PIPE_TEXTURE_2D ||
4567 state->target == PIPE_TEXTURE_RECT || state->target == PIPE_TEXTURE_CUBE)
4568 last_layer = state->u.tex.first_layer;
4571 pipe_format = state->format;
4620 vi_dcc_formats_are_incompatible(texture, state->u.tex.first_level, state->format);
4623 sctx->screen, tex, true, state->target, pipe_format, state_swizzle,
4624 state->u.tex.first_level, state->u.tex.last_level,
4625 state->u.tex.first_layer, last_layer, texture->width0, texture->height0, texture->depth0,
4626 view->state, view->fmask_state);
4633 static void si_sampler_view_destroy(struct pipe_context *ctx, struct pipe_sampler_view *state)
4635 struct si_sampler_view *view = (struct si_sampler_view *)state;
4637 pipe_resource_reference(&state->texture, NULL);
4648 const struct pipe_sampler_state *state,
4651 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4652 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4654 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4655 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4656 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4736 const struct pipe_sampler_state *state)
4741 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso : state->max_anisotropy;
4743 bool trunc_coord = state->min_img_filter == PIPE_TEX_FILTER_NEAREST &&
4744 state->mag_img_filter == PIPE_TEX_FILTER_NEAREST &&
4745 state->compare_mode == PIPE_TEX_COMPARE_NONE;
4753 if (!is_wrap_mode_legal(sscreen, state->wrap_s) ||
4754 !is_wrap_mode_legal(sscreen, state->wrap_t) ||
4755 !is_wrap_mode_legal(sscreen, state->wrap_r) ||
4757 (state->min_mip_filter != PIPE_TEX_MIPFILTER_NONE ||
4758 state->max_anisotropy > 0))) {
4767 (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4768 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4769 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4770 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4772 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4775 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4776 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4778 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4779 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4780 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4781 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
4782 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color,
4783 state->border_color_is_integer);
4799 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4802 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4807 si_translate_border_color(sctx, state, &clamped_border_color, false);
4843 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4846 struct si_sampler_state *s = state;
4851 free(state);
5085 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
5089 struct si_vertex_elements *v = (struct si_vertex_elements *)state;
5134 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
5137 struct si_vertex_elements *v = (struct si_vertex_elements *)state;
5139 if (sctx->vertex_elements == state)
5143 FREE(state);
5232 struct si_vertex_state *state = CALLOC_STRUCT(si_vertex_state);
5235 &state->b);
5237 /* Initialize the vertex element state in state->element.
5238 * Do it by creating a vertex element state object and copying it there.
5243 state->velems = *velems;
5246 assert(!state->velems.instance_divisor_is_one);
5247 assert(!state->velems.instance_divisor_is_fetched);
5248 assert(!state->velems.fix_fetch_always);
5258 si_set_vertex_buffer_descriptor(sscreen, &state->velems, &state->b.input.vbuffer, i,
5259 &state->descriptors[i * 4]);
5262 return &state->b;
5266 struct pipe_vertex_state *state)
5268 pipe_vertex_buffer_unreference(&state->input.vbuffer);
5269 pipe_resource_reference(&state->input.indexbuf, NULL);
5270 FREE(state);
5288 struct pipe_vertex_state *state)
5292 util_vertex_state_destroy(screen, &sscreen->vertex_state_cache, state);