Lines Matching refs:sscreen
400 static void si_blend_check_commutativity(struct si_screen *sscreen, struct si_state_blend *blend,
932 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
1052 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.gfx_level >= GFX9));
1070 S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.gfx_level >= GFX10 ?
1823 struct si_screen *sscreen = (struct si_screen *)screen;
1827 assert(sscreen->info.gfx_level <= GFX9);
1843 if (sscreen->info.gfx_level <= GFX8)
1897 (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA10 ||
1898 sscreen->info.family == CHIP_RAVEN || sscreen->info.family == CHIP_RAVEN2)) {
2164 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex, unsigned view_target,
2177 sscreen->info.gfx_level == GFX9 &&
2210 struct si_screen *sscreen = (struct si_screen *)screen;
2218 if (sscreen->info.gfx_level >= GFX10) {
2219 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[format];
2343 struct si_screen *sscreen = (struct si_screen *)screen;
2369 if (sscreen->info.gfx_level >= GFX10) {
2370 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[format];
2400 struct si_screen *sscreen = (struct si_screen *)screen;
2415 !sscreen->info.has_3d_cube_border_color_mipmap)
2436 const unsigned max_eqaa_samples = util_bitcount(sscreen->info.enabled_rb_mask) <= 1 ? 8 : 16;
2443 if (!sscreen->info.has_eqaa_surface_allocator || util_format_is_depth_or_stencil(format)) {
2466 si_is_colorbuffer_format_supported(sscreen->info.gfx_level, format)) {
4739 struct si_screen *sscreen = sctx->screen;
4741 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso : state->max_anisotropy;
4753 if (!is_wrap_mode_legal(sscreen, state->wrap_s) ||
4754 !is_wrap_mode_legal(sscreen, state->wrap_t) ||
4755 !is_wrap_mode_legal(sscreen, state->wrap_r) ||
4756 (!sscreen->info.has_3d_cube_border_color_mipmap &&
4785 if (sscreen->info.gfx_level >= GFX10) {
4803 if (sscreen->info.gfx_level <= GFX9)
4874 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
4891 unsigned num_vbos_in_user_sgprs = si_num_vbos_in_user_sgprs(sscreen);
4984 always_fix = sscreen->info.gfx_level <= GFX8 && sscreen->info.family != CHIP_STONEY &&
5029 (sscreen->info.gfx_level == GFX6 || sscreen->info.gfx_level >= GFX10);
5030 bool opencode = sscreen->options.vs_fetch_always_opencode;
5056 if (sscreen->info.gfx_level >= GFX10) {
5057 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[elements[i].src_format];
5060 S_008F0C_RESOURCE_LEVEL(sscreen->info.gfx_level < GFX11);
5073 &sscreen->b, 0, PIPE_USAGE_DEFAULT, num_divisors * sizeof(divisor_factors[0]));
5079 sscreen->ws->buffer_map(sscreen->ws, v->instance_divisor_factor_buffer->buf, NULL, PIPE_MAP_WRITE);
5231 struct si_screen *sscreen = (struct si_screen *)screen;
5258 si_set_vertex_buffer_descriptor(sscreen, &state->velems, &state->b.input.vbuffer, i,
5281 struct si_screen *sscreen = (struct si_screen *)screen;
5284 full_velem_mask, &sscreen->vertex_state_cache);
5290 struct si_screen *sscreen = (struct si_screen *)screen;
5292 util_vertex_state_destroy(screen, &sscreen->vertex_state_cache, state);
5469 void si_init_screen_state_functions(struct si_screen *sscreen)
5471 sscreen->b.is_format_supported = si_is_format_supported;
5472 sscreen->b.create_vertex_state = si_pipe_create_vertex_state;
5473 sscreen->b.vertex_state_destroy = si_pipe_vertex_state_destroy;
5475 if (sscreen->info.gfx_level >= GFX10) {
5476 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
5478 sscreen->make_texture_descriptor = si_make_texture_descriptor;
5481 util_vertex_state_cache_init(&sscreen->vertex_state_cache,
5522 struct si_screen *sscreen = sctx->screen;
5523 unsigned num_rb = MIN2(sscreen->info.max_render_backends, 16);
5524 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5525 unsigned raster_config = sscreen->pa_sc_raster_config;
5526 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5540 unsigned gfx103_get_cu_mask_ps(struct si_screen *sscreen)
5549 return u_bit_consecutive(0, sscreen->info.min_good_cu_per_sa);
5554 struct si_screen *sscreen = sctx->screen;
5556 bool has_clear_state = sscreen->info.has_clear_state;
5575 if (sscreen->dpbb_allowed) {
5652 cu_mask_ps = gfx103_get_cu_mask_ps(sscreen);
5659 C_00B01C_CU_EN, 0, &sscreen->info,
5679 if (sscreen->info.gfx_level >= GFX10) {
5681 S_00B524_MEM_BASE(sscreen->info.address32_hi >> 8));
5683 S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8));
5684 } else if (sscreen->info.gfx_level == GFX9) {
5686 S_00B414_MEM_BASE(sscreen->info.address32_hi >> 8));
5688 S_00B214_MEM_BASE(sscreen->info.address32_hi >> 8));
5691 S_00B524_MEM_BASE(sscreen->info.address32_hi >> 8));
5697 C_00B51C_CU_EN, 0, &sscreen->info, (void*)si_pm4_set_reg);
5701 C_00B31C_CU_EN, 0, &sscreen->info, (void*)si_pm4_set_reg);
5743 if (sscreen->info.gfx_level <= GFX9) {
5760 0, &sscreen->info,
5764 S_028C48_MAX_ALLOC_COUNT(sscreen->info.pbb_max_alloc_count - 1) |
5799 if (sscreen->info.max_render_backends <= 4) {
5856 sscreen->info.pa_sc_tile_steering_override);
5870 C_00B004_CU_EN, 16, &sscreen->info, (void*)si_pm4_set_reg_idx3);
5872 C_00B104_CU_EN, 16, &sscreen->info, (void*)si_pm4_set_reg_idx3);
5874 C_00B404_CU_EN, 16, &sscreen->info, (void*)si_pm4_set_reg_idx3);
5934 assert((sscreen->attribute_ring->gpu_address >> 32) == sscreen->info.address32_hi);
5938 sscreen->attribute_ring->gpu_address >> 16);
5940 S_03111C_MEM_SIZE(((sscreen->attribute_ring->bo_size /
5941 sscreen->info.max_se) >> 16) - 1) |
5942 S_03111C_BIG_PAGE(sscreen->info.discardable_allows_big_page) |