Lines Matching refs:sctx
71 static void si_emit_cb_render_state(struct si_context *sctx)
73 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
74 struct si_state_blend *blend = sctx->queued.named.blend;
77 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_mask;
86 if (blend->dual_src_blend && sctx->shader.ps.cso &&
87 (sctx->shader.ps.cso->info.colors_written & 0x3) != 0x3)
93 if (sctx->screen->dpbb_allowed && sctx->last_cb_target_mask != cb_target_mask) {
94 sctx->last_cb_target_mask = cb_target_mask;
103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
106 if (sctx->gfx_level >= GFX8) {
112 blend->dcc_msaa_corruption_4bit & cb_target_mask && sctx->framebuffer.nr_samples >= 2;
114 if (sctx->gfx_level >= GFX11) {
115 radeon_opt_set_context_reg(sctx, R_028424_CB_FDCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
120 sctx, R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->gfx_level <= GFX9) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(sctx->gfx_level >= GFX10 ? 6 : 4) |
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->gfx_level < GFX11 &&
125 sctx->screen->info.has_dcc_constant_encode));
130 if (sctx->screen->info.rbplus_allowed) {
132 sctx->shader.ps.cso ? sctx->shader.ps.current->key.ps.part.epilog.spi_shader_col_format
138 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
139 struct si_surface *surf = (struct si_surface *)sctx->framebuffer.state.cbufs[i];
153 format = sctx->gfx_level >= GFX11 ? G_028C70_FORMAT_GFX11(surf->cb_color_info):
160 has_alpha = !(sctx->gfx_level >= GFX11 ? G_028C74_FORCE_DST_ALPHA_1_GFX11(surf->cb_color_attrib):
269 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
272 radeon_end_update_context_roll(sctx);
442 struct si_context *sctx = (struct si_context *)ctx;
517 if (sctx->gfx_level >= GFX11)
547 si_blend_check_commutativity(sctx->screen, blend, eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
548 si_blend_check_commutativity(sctx->screen, blend, eqA, srcA, dstA, 0x8 << (4 * i));
590 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(sctx->gfx_level, srcRGB));
591 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(sctx->gfx_level, dstRGB));
596 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(sctx->gfx_level, srcA));
597 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(sctx->gfx_level, dstA));
604 if (sctx->gfx_level >= GFX8 && sctx->gfx_level <= GFX10)
615 if (sctx->gfx_level >= GFX8 && sctx->gfx_level <= GFX10 && logicop_enable)
624 if (sctx->screen->info.rbplus_allowed) {
652 static bool si_check_blend_dst_sampler_noop(struct si_context *sctx)
654 if (sctx->framebuffer.state.nr_cbufs == 1) {
655 struct si_shader_selector *sel = sctx->shader.ps.cso;
683 int unit = sctx->shader.ps.cso->info.writes_1_if_tex_is_1 - 1;
684 struct si_samplers *samp = &sctx->samplers[PIPE_SHADER_FRAGMENT];
706 struct si_context *sctx = (struct si_context *)ctx;
708 if (!si_check_blend_dst_sampler_noop(sctx))
711 sctx->real_draw_vbo(ctx, info, drawid_offset, indirect, draws, num_draws);
720 struct si_context *sctx = (struct si_context *)ctx;
722 if (!si_check_blend_dst_sampler_noop(sctx))
725 sctx->real_draw_vertex_state(ctx, state, partial_velem_mask, info, draws, num_draws);
730 struct si_context *sctx = (struct si_context *)ctx;
731 struct si_state_blend *old_blend = sctx->queued.named.blend;
735 blend = (struct si_state_blend *)sctx->noop_blend;
737 si_pm4_bind_state(sctx, blend, blend);
742 sctx->framebuffer.has_dcc_msaa))
743 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
745 if (sctx->screen->info.has_export_conflict_bug &&
747 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
755 si_ps_key_update_framebuffer_blend(sctx);
756 si_ps_key_update_blend_rasterizer(sctx);
757 si_update_ps_inputs_read_or_disabled(sctx);
758 sctx->do_update_shaders = true;
761 if (sctx->screen->dpbb_allowed &&
765 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
767 if (sctx->screen->has_out_of_order_rast &&
772 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
774 if (likely(!radeon_uses_secure_bos(sctx->ws))) {
776 si_install_draw_wrapper(sctx, si_draw_blend_dst_sampler_noop,
779 si_install_draw_wrapper(sctx, NULL, NULL);
786 struct si_context *sctx = (struct si_context *)ctx;
788 if (sctx->queued.named.blend == state)
789 si_bind_blend_state(ctx, sctx->noop_blend);
791 si_pm4_free_state(sctx, (struct si_pm4_state*)state, SI_STATE_IDX(blend));
796 struct si_context *sctx = (struct si_context *)ctx;
799 sctx->blend_color = *state;
800 sctx->blend_color_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
801 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
804 static void si_emit_blend_color(struct si_context *sctx)
806 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
810 radeon_emit_array((uint32_t *)sctx->blend_color.color, 4);
820 struct si_context *sctx = (struct si_context *)ctx;
824 if (memcmp(&sctx->clip_state, state, sizeof(*state)) == 0)
827 sctx->clip_state = *state;
828 sctx->clip_state_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
829 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
835 si_set_internal_const_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
838 static void si_emit_clip_state(struct si_context *sctx)
840 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
844 radeon_emit_array((uint32_t *)sctx->clip_state.ucp, 6 * 4);
848 static void si_emit_clip_regs(struct si_context *sctx)
850 struct si_shader *vs = si_get_vs(sctx)->current;
853 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
869 unsigned pa_cl_cntl = S_02881C_BYPASS_VTX_RATE_COMBINER(sctx->gfx_level >= GFX10_3 &&
870 !sctx->screen->options.vrs2x2) |
871 S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx->gfx_level >= GFX10_3) |
874 radeon_begin(&sctx->gfx_cs);
875 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
877 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
879 radeon_end_update_context_roll(sctx);
885 static void si_update_poly_offset_state(struct si_context *sctx)
887 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
889 if (!rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
890 si_pm4_bind_state(sctx, poly_offset, NULL);
897 switch (sctx->framebuffer.state.zsbuf->texture->format) {
899 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
902 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
906 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
1143 struct si_context *sctx = (struct si_context *)ctx;
1144 struct si_state_rasterizer *old_rs = (struct si_state_rasterizer *)sctx->queued.named.rasterizer;
1148 rs = (struct si_state_rasterizer *)sctx->discard_rasterizer_state;
1151 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1152 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1155 if (sctx->screen->info.has_msaa_sample_loc_bug && sctx->framebuffer.nr_samples > 1)
1156 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1159 if (sctx->screen->use_ngg_culling)
1160 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
1164 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1166 if (sctx->screen->use_ngg_culling &&
1169 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
1171 SET_FIELD(sctx->current_vs_state, VS_STATE_CLAMP_VERTEX_COLOR, rs->clamp_vertex_color);
1173 si_pm4_bind_state(sctx, rasterizer, rs);
1174 si_update_poly_offset_state(sctx);
1177 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1181 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1184 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1188 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1192 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
1205 si_ps_key_update_blend_rasterizer(sctx);
1206 si_ps_key_update_rasterizer(sctx);
1207 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
1208 si_update_ps_inputs_read_or_disabled(sctx);
1209 sctx->do_update_shaders = true;
1217 si_update_vrs_flat_shading(sctx);
1222 struct si_context *sctx = (struct si_context *)ctx;
1225 if (sctx->queued.named.rasterizer == state)
1226 si_bind_rs_state(ctx, sctx->discard_rasterizer_state);
1229 si_pm4_free_state(sctx, &rs->pm4, SI_STATE_IDX(rasterizer));
1235 static void si_emit_stencil_ref(struct si_context *sctx)
1237 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1238 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1239 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1256 struct si_context *sctx = (struct si_context *)ctx;
1258 if (memcmp(&sctx->stencil_ref.state, &state, sizeof(state)) == 0)
1261 sctx->stencil_ref.state = state;
1262 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1412 struct si_context *sctx = (struct si_context *)ctx;
1413 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1417 dsa = (struct si_state_dsa *)sctx->noop_dsa;
1419 si_pm4_bind_state(sctx, dsa, dsa);
1421 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1423 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1424 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1428 si_ps_key_update_dsa(sctx);
1429 si_update_ps_inputs_read_or_disabled(sctx);
1430 sctx->do_update_shaders = true;
1433 if (sctx->screen->dpbb_allowed && ((old_dsa->depth_enabled != dsa->depth_enabled ||
1436 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1438 if (sctx->screen->has_out_of_order_rast &&
1441 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1446 struct si_context *sctx = (struct si_context *)ctx;
1448 if (sctx->queued.named.dsa == state)
1449 si_bind_dsa_state(ctx, sctx->noop_dsa);
1451 si_pm4_free_state(sctx, (struct si_pm4_state*)state, SI_STATE_IDX(dsa));
1454 static void *si_create_db_flush_dsa(struct si_context *sctx)
1458 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1465 struct si_context *sctx = (struct si_context *)ctx;
1469 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1470 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1472 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1473 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1477 if (sctx->occlusion_queries_disabled != !enable) {
1478 sctx->occlusion_queries_disabled = !enable;
1479 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1483 void si_set_occlusion_query_state(struct si_context *sctx, bool old_perfect_enable)
1485 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1487 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1490 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1493 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1495 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1498 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1500 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, true, &st->saved_const0);
1503 static void si_emit_db_render_state(struct si_context *sctx)
1505 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1509 if (sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled) {
1510 db_render_control = S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1511 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1512 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1513 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1514 db_render_control = S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1515 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1517 db_render_control = S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1518 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1521 if (sctx->gfx_level >= GFX11) {
1524 if (sctx->screen->info.has_dedicated_vram) {
1525 if (sctx->framebuffer.nr_samples == 8)
1527 else if (sctx->framebuffer.nr_samples == 4)
1530 if (sctx->framebuffer.nr_samples == 8)
1535 if (sctx->framebuffer.nr_samples >= 4) {
1547 if (sctx->num_occlusion_queries > 0 && !sctx->occlusion_queries_disabled) {
1548 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1549 bool gfx10_perfect = sctx->gfx_level >= GFX10 && perfect;
1551 if (sctx->gfx_level >= GFX7) {
1552 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1560 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1564 if (sctx->gfx_level >= GFX7) {
1571 radeon_begin(&sctx->gfx_cs);
1572 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
1577 sctx, R_028010_DB_RENDER_OVERRIDE2, SI_TRACKED_DB_RENDER_OVERRIDE2,
1578 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1579 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1580 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
1581 S_028010_CENTROID_COMPUTATION_MODE(sctx->gfx_level >= GFX10_3 ? 1 : 0));
1583 db_shader_control = sctx->ps_db_shader_control;
1586 if (sctx->gfx_level == GFX6 && sctx->smoothing_enabled) {
1595 if (sctx->screen->info.has_rbplus && !sctx->screen->info.rbplus_allowed)
1598 if (sctx->screen->info.has_export_conflict_bug &&
1599 sctx->queued.named.blend->blend_enable_4bit &&
1600 si_get_num_coverage_samples(sctx) == 1) {
1605 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1608 if (sctx->gfx_level >= GFX10_3) {
1609 if (sctx->allow_flat_shading) {
1610 if (sctx->gfx_level == GFX11) {
1611 radeon_opt_set_context_reg(sctx, R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
1619 radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
1632 if (sctx->gfx_level == GFX11) {
1633 unsigned mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ?
1636 radeon_opt_set_context_reg(sctx, R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
1641 unsigned mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ?
1644 radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
1652 radeon_end_update_context_roll(sctx);
2512 static void si_initialize_color_surface(struct si_context *sctx, struct si_surface *surf)
2550 format = si_translate_colorformat(sctx->gfx_level, surf->base.format);
2555 swap = si_translate_colorswap(sctx->gfx_level, surf->base.format, false);
2588 if (sctx->gfx_level >= GFX11) {
2596 color_attrib = sctx->gfx_level >= GFX11 ?
2604 if (sctx->gfx_level >= GFX11) {
2613 if (sctx->gfx_level == GFX6) {
2626 if (!sctx->screen->info.has_dedicated_vram)
2629 if (sctx->gfx_level >= GFX10) {
2634 if (sctx->gfx_level >= GFX11)
2638 } else if (sctx->gfx_level >= GFX8) {
2654 if (!tex->surface.fmask_size && sctx->gfx_level == GFX6) {
2666 if (sctx->gfx_level >= GFX10) {
2671 S_028EE0_RESOURCE_LEVEL(sctx->gfx_level >= GFX11 ? 0 : 1);
2672 } else if (sctx->gfx_level == GFX9) {
2678 if (sctx->gfx_level >= GFX9) {
2694 static void si_init_depth_surface(struct si_context *sctx, struct si_surface *surf)
2713 if (sctx->gfx_level >= GFX10) {
2718 if (sctx->gfx_level >= GFX9) {
2726 S_028040_ITERATE_256(sctx->gfx_level >= GFX11);
2729 S_028044_ITERATE_256(sctx->gfx_level >= GFX11);
2731 if (sctx->gfx_level == GFX9) {
2753 if (sctx->gfx_level == GFX9) {
2773 if (sctx->gfx_level >= GFX7) {
2774 struct radeon_info *info = &sctx->screen->info;
2833 void si_set_sampler_depth_decompress_mask(struct si_context *sctx, struct si_texture *tex)
2838 u_foreach_bit(sh, sctx->shader_has_depth_tex) {
2839 u_foreach_bit(i, sctx->samplers[sh].has_depth_tex_mask) {
2840 if (sctx->samplers[sh].views[i]->texture == &tex->buffer.b.b) {
2841 sctx->samplers[sh].needs_depth_decompress_mask |= 1 << i;
2842 sctx->shader_needs_decompress_mask |= 1 << sh;
2848 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2850 if (sctx->decompression_enabled)
2853 if (sctx->framebuffer.state.zsbuf) {
2854 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2862 si_set_sampler_depth_decompress_mask(sctx, tex);
2865 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2868 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2893 void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex)
2899 struct hash_entry *entry = _mesa_hash_table_search(sctx->dirty_implicit_resources, tex);
2903 _mesa_hash_table_insert(sctx->dirty_implicit_resources, tex, tex);
2909 static void si_update_display_dcc_dirty(struct si_context *sctx)
2911 const struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2915 si_mark_display_dcc_dirty(sctx, (struct si_texture *)state->cbufs[i]->texture);
2922 struct si_context *sctx = (struct si_context *)ctx;
2925 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2926 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2927 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2928 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2931 ((struct si_texture *)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2943 si_update_fb_dirtiness_after_rendering(sctx);
2957 if (!si_texture_disable_dcc(sctx, tex))
2958 si_decompress_dcc(sctx, tex);
2983 if (sctx->framebuffer.uncompressed_cb_mask) {
2984 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2985 sctx->framebuffer.CB_has_shader_readable_metadata,
2986 sctx->framebuffer.all_DCC_pipe_aligned);
2989 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_PS_PARTIAL_FLUSH;
2997 if (sctx->generate_mipmap_for_depth) {
2998 si_make_DB_shader_coherent(sctx, 1, false, sctx->framebuffer.DB_has_shader_readable_metadata);
2999 } else if (sctx->gfx_level == GFX9) {
3006 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
3012 sctx->framebuffer.dirty_cbufs |=
3013 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
3014 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
3016 si_dec_framebuffer_counters(&sctx->framebuffer.state);
3017 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
3019 sctx->framebuffer.colorbuf_enabled_4bit = 0;
3020 sctx->framebuffer.spi_shader_col_format = 0;
3021 sctx->framebuffer.spi_shader_col_format_alpha = 0;
3022 sctx->framebuffer.spi_shader_col_format_blend = 0;
3023 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
3024 sctx->framebuffer.color_is_int8 = 0;
3025 sctx->framebuffer.color_is_int10 = 0;
3027 sctx->framebuffer.compressed_cb_mask = 0;
3028 sctx->framebuffer.uncompressed_cb_mask = 0;
3029 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
3030 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
3031 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
3032 sctx->framebuffer.any_dst_linear = false;
3033 sctx->framebuffer.CB_has_shader_readable_metadata = false;
3034 sctx->framebuffer.DB_has_shader_readable_metadata = false;
3035 sctx->framebuffer.all_DCC_pipe_aligned = true;
3036 sctx->framebuffer.has_dcc_msaa = false;
3037 sctx->framebuffer.min_bytes_per_pixel = 0;
3047 si_initialize_color_surface(sctx, surf);
3050 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
3051 sctx->framebuffer.spi_shader_col_format |= surf->spi_shader_col_format << (i * 4);
3052 sctx->framebuffer.spi_shader_col_format_alpha |= surf->spi_shader_col_format_alpha << (i * 4);
3053 sctx->framebuffer.spi_shader_col_format_blend |= surf->spi_shader_col_format_blend << (i * 4);
3054 sctx->framebuffer.spi_shader_col_format_blend_alpha |= surf->spi_shader_col_format_blend_alpha
3058 sctx->framebuffer.color_is_int8 |= 1 << i;
3060 sctx->framebuffer.color_is_int10 |= 1 << i;
3063 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3065 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
3072 sctx->framebuffer.nr_color_samples =
3073 MIN2(sctx->framebuffer.nr_color_samples, tex->buffer.b.b.nr_storage_samples);
3074 sctx->framebuffer.nr_color_samples = MAX2(1, sctx->framebuffer.nr_color_samples);
3078 sctx->framebuffer.any_dst_linear = true;
3081 sctx->framebuffer.CB_has_shader_readable_metadata = true;
3083 if (sctx->gfx_level >= GFX9 && !tex->surface.u.gfx9.color.dcc.pipe_aligned)
3084 sctx->framebuffer.all_DCC_pipe_aligned = false;
3087 sctx->framebuffer.has_dcc_msaa = true;
3090 si_context_add_resource_size(sctx, surf->base.texture);
3095 if (!sctx->framebuffer.min_bytes_per_pixel ||
3096 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3097 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
3107 si_init_depth_surface(sctx, surf);
3111 sctx->framebuffer.DB_has_shader_readable_metadata = true;
3113 si_context_add_resource_size(sctx, surf->base.texture);
3116 if (!sctx->framebuffer.min_bytes_per_pixel ||
3117 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3118 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
3121 si_update_ps_colorbuf0_slot(sctx);
3122 si_update_poly_offset_state(sctx);
3123 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3124 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
3127 if (sctx->screen->use_ngg_culling)
3128 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
3130 if (sctx->screen->dpbb_allowed)
3131 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3133 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
3134 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3136 if (sctx->screen->has_out_of_order_rast &&
3137 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3138 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3140 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3142 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3145 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3146 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3148 if (!sctx->sample_pos_buffer) {
3149 sctx->sample_pos_buffer = pipe_buffer_create_with_data(&sctx->b, 0, PIPE_USAGE_DEFAULT,
3150 sizeof(sctx->sample_positions),
3151 &sctx->sample_positions);
3153 constbuf.buffer = sctx->sample_pos_buffer;
3156 switch (sctx->framebuffer.nr_samples) {
3162 (ubyte *)sctx->sample_positions.x2 - (ubyte *)sctx->sample_positions.x1;
3166 (ubyte *)sctx->sample_positions.x4 - (ubyte *)sctx->sample_positions.x1;
3170 (ubyte *)sctx->sample_positions.x8 - (ubyte *)sctx->sample_positions.x1;
3174 (ubyte *)sctx->sample_positions.x16 - (ubyte *)sctx->sample_positions.x1;
3177 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx->framebuffer.nr_samples);
3180 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3181 si_set_internal_const_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3183 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3186 si_ps_key_update_framebuffer(sctx);
3187 si_ps_key_update_framebuffer_blend(sctx);
3188 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
3189 si_update_ps_inputs_read_or_disabled(sctx);
3190 sctx->do_update_shaders = true;
3192 if (!sctx->decompression_enabled) {
3196 sctx->need_check_render_feedback = true;
3200 static void si_emit_framebuffer_state(struct si_context *sctx)
3202 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3203 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3216 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3222 sctx->gfx_level >= GFX11 ?
3230 sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC |
3234 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, tex->cmask_buffer,
3261 if (sctx->gfx_level < GFX11 && cb->base.u.tex.level > 0)
3276 assert(!is_msaa_resolve_dst || sctx->gfx_level < GFX11);
3278 if (!is_msaa_resolve_dst && sctx->gfx_level < GFX11)
3288 if (sctx->gfx_level >= GFX11) {
3314 } else if (sctx->gfx_level >= GFX10) {
3355 } else if (sctx->gfx_level == GFX9) {
3423 if (sctx->gfx_level >= GFX7)
3431 if (sctx->gfx_level >= GFX7)
3438 sctx->gfx_level >= GFX8 ? 14 : 13);
3453 if (sctx->gfx_level >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3458 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3462 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3469 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE |
3475 if (sctx->gfx_level >= GFX9 && tc_compat_htile) {
3481 if (sctx->gfx_level >= GFX10) {
3489 if (sctx->screen->info.has_two_planes_iterate256_bug && iterate256 &&
3503 if (sctx->gfx_level >= GFX10) {
3507 if (sctx->gfx_level >= GFX11) {
3527 } else if (sctx->gfx_level == GFX9) {
3588 } else if (sctx->framebuffer.dirty_zsbuf) {
3589 if (sctx->gfx_level == GFX9)
3598 S_028040_NUM_SAMPLES(sctx->gfx_level == GFX11 ? sctx->framebuffer.log_samples : 0));
3607 if (sctx->screen->dpbb_allowed) {
3613 si_update_display_dcc_dirty(sctx);
3615 sctx->framebuffer.dirty_cbufs = 0;
3616 sctx->framebuffer.dirty_zsbuf = false;
3619 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3621 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3622 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3623 unsigned nr_samples = sctx->framebuffer.nr_samples;
3624 bool has_msaa_sample_loc_bug = sctx->screen->info.has_msaa_sample_loc_bug;
3629 if (nr_samples <= 1 && sctx->smoothing_enabled)
3638 if ((nr_samples >= 2 || has_msaa_sample_loc_bug || sctx->gfx_level >= GFX10) &&
3639 nr_samples != sctx->sample_locs_num_samples) {
3640 sctx->sample_locs_num_samples = nr_samples;
3646 if (sctx->family >= CHIP_POLARIS10) {
3650 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3663 if (has_msaa_sample_loc_bug && sctx->framebuffer.nr_samples > 1 && !rs->multisample_enable)
3666 radeon_opt_set_context_reg(sctx, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3673 bool exclusion = sctx->gfx_level >= GFX7 && (!rs->multisample_enable || nr_samples != 16);
3675 sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL, SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3680 static bool si_out_of_order_rasterization(struct si_context *sctx)
3682 struct si_state_blend *blend = sctx->queued.named.blend;
3683 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3685 if (!sctx->screen->has_out_of_order_rast)
3688 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3699 if (sctx->framebuffer.state.zsbuf) {
3700 struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
3708 if (sctx->shader.ps.cso && sctx->shader.ps.cso->info.base.writes_memory &&
3709 sctx->shader.ps.cso->info.base.fs.early_fragment_tests &&
3713 if (sctx->num_perfect_occlusion_queries != 0 && !dsa_order_invariant.pass_set)
3737 static void si_emit_msaa_config(struct si_context *sctx)
3739 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3740 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3742 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3743 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3754 S_028804_INTERPOLATE_COMP_Z(sctx->gfx_level < GFX11) |
3757 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3800 coverage_samples = si_get_num_coverage_samples(sctx);
3822 (sctx->family == CHIP_VEGA20 ||
3823 sctx->gfx_level >= GFX10));
3827 S_028BE0_COVERED_CENTROID_IS_CENTER(sctx->gfx_level >= GFX10_3);
3830 if (sctx->framebuffer.nr_samples > 1) {
3831 if (sctx->framebuffer.state.zsbuf) {
3832 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3839 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3841 if (sctx->framebuffer.nr_samples > 1) {
3847 } else if (sctx->smoothing_enabled) {
3855 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_LINE_CNTL,
3858 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA, db_eqaa);
3860 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1, SI_TRACKED_PA_SC_MODE_CNTL_1,
3862 radeon_end_update_context_roll(sctx);
3865 void si_update_ps_iter_samples(struct si_context *sctx)
3867 if (sctx->framebuffer.nr_samples > 1)
3868 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3869 if (sctx->screen->dpbb_allowed)
3870 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3875 struct si_context *sctx = (struct si_context *)ctx;
3880 if (sctx->ps_iter_samples == min_samples)
3883 sctx->ps_iter_samples = min_samples;
3885 si_ps_key_update_sample_shading(sctx);
3886 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
3887 sctx->do_update_shaders = true;
3889 si_update_ps_iter_samples(sctx);
4526 struct si_context *sctx = (struct si_context *)ctx;
4552 uint32_t elements = si_clamp_texture_texel_count(sctx->screen->max_texel_buffer_elements,
4555 si_make_buffer_descriptor(sctx->screen, si_resource(texture), state->format,
4622 sctx->screen->make_texture_descriptor(
4623 sctx->screen, tex, true, state->target, pipe_format, state_swizzle,
4647 static uint32_t si_translate_border_color(struct si_context *sctx,
4679 for (i = 0; i < sctx->border_color_count; i++)
4680 if (memcmp(&sctx->border_color_table[i], color, sizeof(*color)) == 0)
4695 if (i == sctx->border_color_count) {
4697 memcpy(&sctx->border_color_table[i], color, sizeof(*color));
4698 util_memcpy_cpu_to_le32(&sctx->border_color_map[i], color, sizeof(*color));
4699 sctx->border_color_count++;
4702 return (sctx->screen->info.gfx_level >= GFX11 ? S_008F3C_BORDER_COLOR_PTR_GFX11(i):
4738 struct si_context *sctx = (struct si_context *)ctx;
4739 struct si_screen *sscreen = sctx->screen;
4774 S_008F30_COMPAT_MODE(sctx->gfx_level == GFX8 || sctx->gfx_level == GFX9));
4782 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color,
4788 rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->gfx_level <= GFX8) |
4790 S_008F38_ANISO_OVERRIDE_GFX8(sctx->gfx_level >= GFX8);
4807 si_translate_border_color(sctx, state, &clamped_border_color, false);
4815 struct si_context *sctx = (struct si_context *)ctx;
4817 if (sctx->sample_mask == (uint16_t)sample_mask)
4820 sctx->sample_mask = sample_mask;
4821 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4824 static void si_emit_sample_mask(struct si_context *sctx)
4826 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4827 unsigned mask = sctx->sample_mask;
4833 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4834 (mask & 1 && sctx->blitter_running));
5087 struct si_context *sctx = (struct si_context *)ctx;
5088 struct si_vertex_elements *old = sctx->vertex_elements;
5092 v = sctx->no_velems_state;
5094 sctx->vertex_elements = v;
5095 sctx->num_vertex_elements = v->count;
5097 if (sctx->num_vertex_elements) {
5098 sctx->vertex_buffers_dirty = true;
5100 sctx->vertex_buffers_dirty = false;
5101 sctx->vertex_buffer_pointer_dirty = false;
5102 sctx->vertex_buffer_user_sgprs_dirty = false;
5108 sctx->vertex_buffer_unaligned ||
5109 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
5119 si_vs_key_update_inputs(sctx);
5120 sctx->do_update_shaders = true;
5130 si_set_internal_const_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
5136 struct si_context *sctx = (struct si_context *)ctx;
5139 if (sctx->vertex_elements == state)
5140 si_bind_vertex_elements(ctx, sctx->no_velems_state);
5150 struct si_context *sctx = (struct si_context *)ctx;
5151 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
5153 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
5157 assert(start_slot + count + unbind_num_trailing_slots <= ARRAY_SIZE(sctx->vertex_buffer));
5173 si_context_add_resource_size(sctx, buf);
5193 si_context_add_resource_size(sctx, buf);
5206 sctx->vertex_buffers_dirty = sctx->num_vertex_elements > 0;
5207 sctx->vertex_buffer_unaligned = (orig_unaligned & ~updated_mask) | unaligned;
5216 if ((sctx->vertex_elements->vb_alignment_check_mask &
5218 si_vs_key_update_inputs(sctx);
5219 sctx->do_update_shaders = true;
5302 struct si_context *sctx = (struct si_context *)ctx;
5314 si_set_internal_const_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
5319 struct si_context *sctx = (struct si_context *)ctx;
5321 sctx->patch_vertices = patch_vertices;
5326 struct si_context *sctx = (struct si_context *)ctx;
5328 si_update_fb_dirtiness_after_rendering(sctx);
5331 if (sctx->framebuffer.uncompressed_cb_mask) {
5332 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
5333 sctx->framebuffer.CB_has_shader_readable_metadata,
5334 sctx->framebuffer.all_DCC_pipe_aligned);
5341 struct si_context *sctx = (struct si_context *)ctx;
5348 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
5352 sctx->flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
5359 sctx->flags |= SI_CONTEXT_INV_VCACHE;
5362 sctx->screen->info.tcc_rb_non_coherent)
5363 sctx->flags |= SI_CONTEXT_INV_L2;
5370 if (sctx->screen->info.gfx_level <= GFX7)
5371 sctx->flags |= SI_CONTEXT_WB_L2;
5377 if (flags & PIPE_BARRIER_FRAMEBUFFER && sctx->framebuffer.uncompressed_cb_mask) {
5378 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
5380 if (sctx->gfx_level <= GFX8)
5381 sctx->flags |= SI_CONTEXT_WB_L2;
5385 if (sctx->screen->info.gfx_level <= GFX8 && flags & PIPE_BARRIER_INDIRECT_BUFFER)
5386 sctx->flags |= SI_CONTEXT_WB_L2;
5389 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
5396 return si_create_blend_state_mode(&sctx->b, &blend, mode);
5399 void si_init_state_compute_functions(struct si_context *sctx)
5401 sctx->b.create_sampler_state = si_create_sampler_state;
5402 sctx->b.delete_sampler_state = si_delete_sampler_state;
5403 sctx->b.create_sampler_view = si_create_sampler_view;
5404 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
5405 sctx->b.memory_barrier = si_memory_barrier;
5408 void si_init_state_functions(struct si_context *sctx)
5410 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
5411 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
5412 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
5413 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
5414 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
5415 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
5416 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
5417 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
5418 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
5419 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
5420 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
5422 sctx->b.create_blend_state = si_create_blend_state;
5423 sctx->b.bind_blend_state = si_bind_blend_state;
5424 sctx->b.delete_blend_state = si_delete_blend_state;
5425 sctx->b.set_blend_color = si_set_blend_color;
5427 sctx->b.create_rasterizer_state = si_create_rs_state;
5428 sctx->b.bind_rasterizer_state = si_bind_rs_state;
5429 sctx->b.delete_rasterizer_state = si_delete_rs_state;
5431 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
5432 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
5433 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
5435 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
5437 if (sctx->gfx_level < GFX11) {
5438 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
5439 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
5440 sctx->custom_blend_eliminate_fastclear =
5441 si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
5444 sctx->custom_blend_dcc_decompress =
5445 si_create_blend_custom(sctx, sctx->gfx_level >= GFX11 ?
5449 sctx->b.set_clip_state = si_set_clip_state;
5450 sctx->b.set_stencil_ref = si_set_stencil_ref;
5452 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
5454 sctx->b.set_sample_mask = si_set_sample_mask;
5456 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
5457 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
5458 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
5459 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
5461 sctx->b.texture_barrier = si_texture_barrier;
5462 sctx->b.set_min_samples = si_set_min_samples;
5463 sctx->b.set_tess_state = si_set_tess_state;
5464 sctx->b.set_patch_vertices = si_set_patch_vertices;
5466 sctx->b.set_active_query_state = si_set_active_query_state;
5485 static void si_set_grbm_gfx_index(struct si_context *sctx, struct si_pm4_state *pm4, unsigned value)
5487 unsigned reg = sctx->gfx_level >= GFX7 ? R_030800_GRBM_GFX_INDEX : R_00802C_GRBM_GFX_INDEX;
5491 static void si_set_grbm_gfx_index_se(struct si_context *sctx, struct si_pm4_state *pm4, unsigned se)
5493 assert(se == ~0 || se < sctx->screen->info.max_se);
5494 si_set_grbm_gfx_index(sctx, pm4,
5500 static void si_write_harvested_raster_configs(struct si_context *sctx, struct si_pm4_state *pm4,
5503 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5507 ac_get_harvested_configs(&sctx->screen->info, raster_config, &raster_config_1, raster_config_se);
5510 si_set_grbm_gfx_index_se(sctx, pm4, se);
5513 si_set_grbm_gfx_index(sctx, pm4, ~0);
5515 if (sctx->gfx_level >= GFX7) {
5520 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5522 struct si_screen *sscreen = sctx->screen;
5533 if (sctx->gfx_level >= GFX7)
5536 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5552 void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
5554 struct si_screen *sscreen = sctx->screen;
5555 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5604 if (sctx->gfx_level < GFX11) {
5611 if (sctx->gfx_level >= GFX7)
5614 if (sctx->gfx_level == GFX6) {
5619 if (sctx->gfx_level >= GFX7) {
5627 if (sctx->gfx_level <= GFX7 || !has_clear_state) {
5628 if (sctx->gfx_level < GFX11) {
5643 if (sctx->gfx_level >= GFX10 && sctx->gfx_level < GFX11) {
5651 if (sctx->gfx_level >= GFX10_3)
5654 if (sctx->gfx_level >= GFX7) {
5658 S_00B01C_LDS_GROUP_SIZE(sctx->gfx_level >= GFX11),
5660 (void*)(sctx->gfx_level >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg));
5663 if (sctx->gfx_level <= GFX8) {
5664 si_set_raster_config(sctx, pm4);
5694 if (sctx->gfx_level >= GFX7 && sctx->gfx_level <= GFX8) {
5711 if (sctx->gfx_level >= GFX8) {
5714 if (sctx->gfx_level >= GFX11) {
5721 } else if (sctx->gfx_level >= GFX9) {
5727 } else if (sctx->gfx_level == GFX8) {
5736 if (sctx->family == CHIP_FIJI || sctx->family >= CHIP_POLARIS10)
5747 if (sctx->gfx_level == GFX9) {
5757 if (sctx->gfx_level >= GFX9) {
5761 (void*)(sctx->gfx_level >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg));
5771 if (sctx->gfx_level < GFX11) {
5773 sctx->gfx_level >= GFX10 ? 0x20 : 0);
5777 if (sctx->gfx_level >= GFX10) {
5797 unsigned no_alloc = sctx->gfx_level >= GFX11 ? V_02807C_CACHE_NOA_GFX11:
5817 if (sctx->gfx_level >= GFX11)
5847 S_028C50_MAX_DEALLOCS_IN_WAVE(sctx->gfx_level >= GFX11 ? 16 : 512));
5849 if (sctx->gfx_level < GFX11) {
5867 if (sctx->gfx_level >= GFX10 && sctx->gfx_level <= GFX10_3) {
5883 if (sctx->gfx_level >= GFX10_3) {
5899 if (sctx->gfx_level >= GFX11) {
5946 sctx->cs_preamble_state = pm4;
5949 sctx->cs_preamble_state_tmz = (struct si_pm4_state *)CALLOC_STRUCT(si_cs_preamble);
5950 memcpy(sctx->cs_preamble_state_tmz, sctx->cs_preamble_state, sizeof(struct si_cs_preamble));