Lines Matching refs:pm4
444 struct si_pm4_state *pm4 = &blend->pm4;
476 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
482 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
523 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
533 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
543 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
599 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
636 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]);
643 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
934 struct si_pm4_state *pm4 = &rs->pm4;
1018 pm4, R_0286D4_SPI_INTERP_CONTROL_0,
1028 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
1041 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
1045 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
1048 pm4, R_028A48_PA_SC_MODE_CNTL_0,
1058 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
1076 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
1086 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
1107 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
1130 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, pa_su_poly_offset_db_fmt_cntl);
1131 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
1132 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale));
1133 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
1134 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale));
1135 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
1229 si_pm4_free_state(sctx, &rs->pm4, SI_STATE_IDX(rasterizer));
1320 struct si_pm4_state *pm4 = &dsa->pm4;
1364 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1370 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1372 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1374 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth_bounds_min));
1375 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth_bounds_max));
5485 static void si_set_grbm_gfx_index(struct si_context *sctx, struct si_pm4_state *pm4, unsigned value)
5488 si_pm4_set_reg(pm4, reg, value);
5491 static void si_set_grbm_gfx_index_se(struct si_context *sctx, struct si_pm4_state *pm4, unsigned se)
5494 si_set_grbm_gfx_index(sctx, pm4,
5500 static void si_write_harvested_raster_configs(struct si_context *sctx, struct si_pm4_state *pm4,
5510 si_set_grbm_gfx_index_se(sctx, pm4, se);
5511 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
5513 si_set_grbm_gfx_index(sctx, pm4, ~0);
5516 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5520 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5532 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config);
5534 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5536 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5559 struct si_pm4_state pm4;
5562 struct si_pm4_state *pm4 = (struct si_pm4_state *)CALLOC_STRUCT(si_cs_preamble);
5564 if (!pm4)
5568 pm4->max_dw = sizeof(struct si_cs_preamble) - offsetof(struct si_cs_preamble, pm4.pm4);
5571 si_pm4_cmd_add(pm4, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
5572 si_pm4_cmd_add(pm4, CC0_UPDATE_LOAD_ENABLES(1));
5573 si_pm4_cmd_add(pm4, CC1_UPDATE_SHADOW_ENABLES(1));
5576 si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0));
5577 si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
5581 si_pm4_cmd_add(pm4, PKT3(PKT3_CLEAR_STATE, 0, 0));
5582 si_pm4_cmd_add(pm4, 0);
5587 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5588 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5591 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5593 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5596 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5597 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5598 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5599 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5600 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5601 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5602 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5605 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5606 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5610 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5612 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, S_028084_ADDRESS(border_color_va >> 40));
5615 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE,
5620 si_pm4_set_reg(pm4, R_030A00_PA_SU_LINE_STIPPLE_VALUE, 0);
5621 si_pm4_set_reg(pm4, R_030A04_PA_SC_LINE_STIPPLE_STATE, 0);
5623 si_pm4_set_reg(pm4, R_008A60_PA_SU_LINE_STIPPLE_VALUE, 0);
5624 si_pm4_set_reg(pm4, R_008B10_PA_SC_LINE_STIPPLE_STATE, 0);
5629 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5630 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5636 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5637 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5638 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5639 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5644 si_pm4_set_reg(pm4, R_028038_DB_DFSM_CONTROL,
5655 ac_set_reg_cu_en(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5664 si_set_raster_config(sctx, pm4);
5667 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5668 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5674 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5675 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5676 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5680 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS,
5682 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES,
5685 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS,
5687 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES,
5690 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS,
5695 ac_set_reg_cu_en(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5698 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_WAVE_LIMIT(0x3F));
5699 ac_set_reg_cu_en(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5707 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5740 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5744 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5748 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5749 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5750 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5752 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
5758 ac_set_reg_cu_en(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5763 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5766 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5769 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5772 si_pm4_set_reg(pm4, R_0301EC_CP_COHER_START_DELAY,
5778 si_pm4_set_reg(pm4, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 0);
5779 si_pm4_set_reg(pm4, R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1, 0);
5780 si_pm4_set_reg(pm4, R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2, 0);
5781 si_pm4_set_reg(pm4, R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3, 0);
5782 si_pm4_set_reg(pm4, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 0);
5783 si_pm4_set_reg(pm4, R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1, 0);
5784 si_pm4_set_reg(pm4, R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2, 0);
5785 si_pm4_set_reg(pm4, R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3, 0);
5786 si_pm4_set_reg(pm4, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 0);
5787 si_pm4_set_reg(pm4, R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1, 0);
5788 si_pm4_set_reg(pm4, R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2, 0);
5789 si_pm4_set_reg(pm4, R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3, 0);
5791 si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
5807 si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL,
5830 si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
5834 si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
5835 si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
5846 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL,
5851 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5855 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
5860 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
5861 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
5862 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
5863 si_pm4_set_reg(pm4, R_03097C_GE_STEREO_CNTL, 0);
5864 si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0);
5869 ac_set_reg_cu_en(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS, S_00B004_CU_EN(cu_mask_ps >> 16),
5871 ac_set_reg_cu_en(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS, S_00B104_CU_EN(0xffff),
5873 ac_set_reg_cu_en(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS, S_00B404_CU_EN(0xffff),
5876 si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
5877 si_pm4_set_reg(pm4, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 0);
5878 si_pm4_set_reg(pm4, R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1, 0);
5879 si_pm4_set_reg(pm4, R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2, 0);
5880 si_pm4_set_reg(pm4, R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3, 0);
5884 si_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff);
5894 si_pm4_set_reg(pm4, R_028848_PA_CL_VRS_CNTL,
5900 si_pm4_set_reg(pm4, R_028C54_PA_SC_BINNER_CNTL_2, 0);
5901 si_pm4_set_reg(pm4, R_028620_PA_RATE_CNTL,
5907 si_pm4_cmd_add(pm4, PKT3(PKT3_RELEASE_MEM, 6, 0));
5908 si_pm4_cmd_add(pm4, S_490_EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) |
5911 si_pm4_cmd_add(pm4, 0); /* DST_SEL, INT_SEL, DATA_SEL */
5912 si_pm4_cmd_add(pm4, 0); /* ADDRESS_LO */
5913 si_pm4_cmd_add(pm4, 0); /* ADDRESS_HI */
5914 si_pm4_cmd_add(pm4, 0); /* DATA_LO */
5915 si_pm4_cmd_add(pm4, 0); /* DATA_HI */
5916 si_pm4_cmd_add(pm4, 0); /* INT_CTXID */
5919 si_pm4_cmd_add(pm4, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
5920 si_pm4_cmd_add(pm4, S_580_PWS_STAGE_SEL(V_580_CP_ME) |
5924 si_pm4_cmd_add(pm4, 0xffffffff); /* GCR_SIZE */
5925 si_pm4_cmd_add(pm4, 0x01ffffff); /* GCR_SIZE_HI */
5926 si_pm4_cmd_add(pm4, 0); /* GCR_BASE_LO */
5927 si_pm4_cmd_add(pm4, 0); /* GCR_BASE_HI */
5928 si_pm4_cmd_add(pm4, S_585_PWS_ENA(1));
5929 si_pm4_cmd_add(pm4, 0); /* GCR_CNTL */
5931 si_pm4_set_reg(pm4, R_031110_SPI_GS_THROTTLE_CNTL1, 0x12355123);
5932 si_pm4_set_reg(pm4, R_031114_SPI_GS_THROTTLE_CNTL2, 0x1544D);
5937 si_pm4_set_reg(pm4, R_031118_SPI_ATTRIBUTE_RING_BASE,
5939 si_pm4_set_reg(pm4, R_03111C_SPI_ATTRIBUTE_RING_SIZE,
5946 sctx->cs_preamble_state = pm4;