Lines Matching defs:tex
686 struct si_texture* tex = (struct si_texture*) samp->views[unit]->texture;
687 if (tex->is_depth &&
688 tex->depth_cleared_level_mask & BITFIELD_BIT(samp->views[unit]->u.tex.first_level) &&
689 tex->depth_clear_value[0] == 1) {
2164 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex, unsigned view_target,
2167 unsigned res_target = tex->buffer.b.b.target;
2178 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
2514 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2600 if (tex->buffer.b.b.nr_samples > 1) {
2601 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2602 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2609 if (tex->surface.fmask_offset) {
2611 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.color.fmask.bankh);
2631 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) |
2633 S_028C78_INDEPENDENT_64B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_64B_blocks);
2635 surf->cb_dcc_control |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX11(tex->surface.u.gfx9.color.dcc.independent_128B_blocks);
2637 surf->cb_dcc_control |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX10(tex->surface.u.gfx9.color.dcc.independent_128B_blocks);
2641 if (tex->buffer.b.b.nr_storage_samples > 1) {
2642 if (tex->surface.bpe == 1)
2644 else if (tex->surface.bpe == 2)
2654 if (!tex->surface.fmask_size && sctx->gfx_level == GFX6) {
2655 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2660 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2661 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2664 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2667 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2670 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2673 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2675 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2681 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2689 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2696 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2697 unsigned level = surf->base.u.tex.level;
2701 format = si_translate_dbformat(tex->db_render_format);
2702 stencil_format = tex->surface.has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2706 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2708 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2709 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2714 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2715 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2719 assert(tex->surface.u.gfx9.surf_offset == 0);
2720 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2721 surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.zs.stencil_offset) >> 8;
2723 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2724 S_028038_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
2725 S_028038_MAXMIP(tex->buffer.b.b.last_level) |
2728 S_02803C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode) |
2732 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.epitch);
2733 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.zs.stencil_epitch);
2737 S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) | S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2739 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2741 s_info |= S_02803C_TILE_STENCIL_DISABLE(tex->htile_stencil_disabled);
2743 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2747 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2750 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
2759 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2764 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.level[level].offset_256B;
2766 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.zs.stencil_level[level].offset_256B;
2769 S_028040_FORMAT(format) | S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2775 unsigned index = tex->surface.u.legacy.tiling_index[level];
2776 unsigned stencil_index = tex->surface.u.legacy.zs.stencil_tiling_index[level];
2777 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2791 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2793 tile_mode_index = si_tile_mode_index(tex, level, true);
2802 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2804 s_info |= S_028044_TILE_STENCIL_DISABLE(tex->htile_stencil_disabled);
2806 if (tex->surface.has_stencil) {
2818 if (tex->buffer.b.b.nr_samples <= 1)
2822 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
2833 void si_set_sampler_depth_decompress_mask(struct si_context *sctx, struct si_texture *tex)
2840 if (sctx->samplers[sh].views[i]->texture == &tex->buffer.b.b) {
2855 struct si_texture *tex = (struct si_texture *)surf->texture;
2857 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2859 if (tex->surface.has_stencil)
2860 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2862 si_set_sampler_depth_decompress_mask(sctx, tex);
2869 struct si_texture *tex = (struct si_texture *)surf->texture;
2871 if (tex->surface.fmask_offset) {
2872 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2873 tex->fmask_is_identity = false;
2882 struct si_texture *tex;
2887 tex = (struct si_texture *)surf->base.texture;
2889 p_atomic_dec(&tex->framebuffers_bound);
2893 void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex)
2895 if (!tex->surface.display_dcc_offset || tex->displayable_dcc_dirty)
2898 if (!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
2899 struct hash_entry *entry = _mesa_hash_table_search(sctx->dirty_implicit_resources, tex);
2902 pipe_resource_reference(&dummy, &tex->buffer.b.b);
2903 _mesa_hash_table_insert(sctx->dirty_implicit_resources, tex, tex);
2906 tex->displayable_dcc_dirty = true;
2924 struct si_texture *tex;
2951 tex = (struct si_texture *)surf->base.texture;
2956 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2957 if (!si_texture_disable_dcc(sctx, tex))
2958 si_decompress_dcc(sctx, tex);
3044 tex = (struct si_texture *)surf->base.texture;
3062 if (tex->surface.fmask_offset)
3070 if (tex->buffer.b.b.nr_samples >= 2 &&
3071 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
3073 MIN2(sctx->framebuffer.nr_color_samples, tex->buffer.b.b.nr_storage_samples);
3077 if (tex->surface.is_linear)
3080 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3083 if (sctx->gfx_level >= GFX9 && !tex->surface.u.gfx9.color.dcc.pipe_aligned)
3086 if (tex->buffer.b.b.nr_storage_samples >= 2)
3092 p_atomic_inc(&tex->framebuffers_bound);
3096 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
3097 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
3110 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level, PIPE_MASK_ZS))
3205 struct si_texture *tex = NULL;
3228 tex = (struct si_texture *)cb->base.texture;
3230 sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC |
3231 (tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
3233 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3234 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, tex->cmask_buffer,
3240 cb_color_base = tex->buffer.gpu_address >> 8;
3242 cb_color_cmask = tex->cmask_base_address_reg;
3244 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3247 if (tex->swap_rgb_to_bgr) {
3261 if (sctx->gfx_level < GFX11 && cb->base.u.tex.level > 0)
3264 if (tex->surface.fmask_offset) {
3265 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
3266 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3270 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3281 cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
3283 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
3284 dcc_tile_swizzle &= ((1 << tex->surface.meta_alignment_log2) - 1) >> 8;
3292 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3293 cb_color_base |= tex->surface.tile_swizzle;
3296 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
3297 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned);
3300 S_028C78_FDCC_ENABLE(vi_dcc_enabled(tex, cb->base.u.tex.level));
3318 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3319 cb_color_base |= tex->surface.tile_swizzle;
3320 if (!tex->surface.fmask_offset)
3322 if (cb->base.u.tex.level > 0)
3326 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
3327 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) |
3329 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned);
3343 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3344 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3361 if (!tex->is_depth && tex->surface.meta_offset)
3362 meta = tex->surface.u.gfx9.color.dcc;
3365 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3366 cb_color_base |= tex->surface.tile_swizzle;
3367 if (!tex->surface.fmask_offset)
3369 if (cb->base.u.tex.level > 0)
3371 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
3372 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) |
3388 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3389 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3394 S_0287A0_EPITCH(tex->surface.u.gfx9.epitch));
3398 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3405 cb_color_base |= tex->surface.tile_swizzle;
3407 if (!tex->surface.fmask_offset)
3409 if (cb->base.u.tex.level > 0)
3412 cb_dcc_base += tex->surface.u.legacy.color.dcc_level[cb->base.u.tex.level].dcc_offset >> 8;
3416 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3422 if (tex->surface.fmask_offset) {
3425 S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.color.fmask.pitch_in_pixels / 8 - 1);
3427 S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.color.fmask.tiling_index);
3428 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.color.fmask.slice_tile_max);
3447 radeon_emit(tex->surface.u.legacy.color.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3450 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3451 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3464 struct si_texture *tex = (struct si_texture *)zb->base.texture;
3469 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE |
3472 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS);
3478 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM && tex->buffer.b.b.nr_samples > 1)
3482 bool iterate256 = tex->buffer.b.b.nr_samples >= 2;
3485 db_stencil_info |= S_028044_ITERATE_FLUSH(!tex->htile_stencil_disabled) |
3490 !tex->htile_stencil_disabled && tex->buffer.b.b.nr_samples == 4) {
3501 unsigned level = zb->base.u.tex.level;
3514 S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
3535 S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
3552 if (si_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS)) {
3553 if (tex->tc_compatible_htile) {
3557 if (tex->buffer.b.b.nr_samples <= 1)
3559 else if (tex->buffer.b.b.nr_samples <= 4)
3570 S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile));
3572 S_028040_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
3583 radeon_emit(tex->stencil_clear_value[level]); /* R_028028_DB_STENCIL_CLEAR */
3584 radeon_emit(fui(tex->depth_clear_value[level])); /* R_02802C_DB_DEPTH_CLEAR */
4006 struct si_screen *screen, struct si_texture *tex, bool sampler, enum pipe_texture_target target,
4011 struct pipe_resource *res = &tex->buffer.b.b;
4048 if (tex->upgraded_depth && !is_stencil) {
4067 type = si_tex_dim(screen, tex, target, res->nr_samples);
4102 tex->buffer.b.b.last_level;
4112 if (vi_dcc_enabled(tex, first_level)) {
4114 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) |
4119 if (tex->surface.fmask_offset) {
4122 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4169 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4177 S_00A00C_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) |
4178 S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
4189 static void si_make_texture_descriptor(struct si_screen *screen, struct si_texture *tex,
4197 struct pipe_resource *res = &tex->buffer.b.b;
4326 type = si_tex_dim(screen, tex, target, num_samples);
4366 : tex->buffer.b.b.last_level);
4373 if (vi_dcc_enabled(tex, first_level)) {
4388 if (tex->surface.fmask_offset) {
4391 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4487 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4494 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4501 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode);
4503 S_008F20_DEPTH(last_layer) | S_008F20_PITCH(tex->surface.u.gfx9.color.fmask_epitch);
4507 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.color.fmask.tiling_index);
4509 S_008F20_PITCH(tex->surface.u.legacy.color.fmask.pitch_in_pixels - 1);
4528 struct si_texture *tex = (struct si_texture *)texture;
4530 unsigned last_layer = state->u.tex.last_layer;
4568 last_layer = state->u.tex.first_layer;
4574 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4575 if (!tex->flushed_depth_texture && !si_init_flushed_depth_texture(ctx, texture)) {
4581 assert(tex->flushed_depth_texture);
4586 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4587 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4589 tex = tex->flushed_depth_texture;
4592 surflevel = tex->surface.u.legacy.level;
4594 if (tex->db_compatible) {
4596 pipe_format = tex->db_render_format;
4613 surflevel = tex->surface.u.legacy.zs.stencil_level;
4620 vi_dcc_formats_are_incompatible(texture, state->u.tex.first_level, state->format);
4623 sctx->screen, tex, true, state->target, pipe_format, state_swizzle,
4624 state->u.tex.first_level, state->u.tex.last_level,
4625 state->u.tex.first_layer, last_layer, texture->width0, texture->height0, texture->depth0,