Lines Matching defs:surf
139 struct si_surface *surf = (struct si_surface *)sctx->framebuffer.state.cbufs[i];
143 if (!surf) {
153 format = sctx->gfx_level >= GFX11 ? G_028C70_FORMAT_GFX11(surf->cb_color_info):
154 G_028C70_FORMAT_GFX6(surf->cb_color_info);
155 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
160 has_alpha = !(sctx->gfx_level >= GFX11 ? G_028C74_FORCE_DST_ALPHA_1_GFX11(surf->cb_color_attrib):
161 G_028C74_FORCE_DST_ALPHA_1_GFX6(surf->cb_color_attrib));
2499 static void si_choose_spi_color_formats(struct si_surface *surf, unsigned format, unsigned swap,
2506 surf->spi_shader_col_format = formats.normal;
2507 surf->spi_shader_col_format_alpha = formats.alpha;
2508 surf->spi_shader_col_format_blend = formats.blend;
2509 surf->spi_shader_col_format_blend_alpha = formats.blend_alpha;
2512 static void si_initialize_color_surface(struct si_context *sctx, struct si_surface *surf)
2514 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2521 desc = util_format_description(surf->base.format);
2550 format = si_translate_colorformat(sctx->gfx_level, surf->base.format);
2552 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2555 swap = si_translate_colorswap(sctx->gfx_level, surf->base.format, false);
2575 surf->color_is_int8 = true;
2577 surf->color_is_int10 = true;
2597 S_028C74_FORCE_DST_ALPHA_1_GFX11(desc->swizzle[3] == PIPE_SWIZZLE_1 || util_format_is_intensity(surf->base.format)):
2598 S_028C74_FORCE_DST_ALPHA_1_GFX6(desc->swizzle[3] == PIPE_SWIZZLE_1 || util_format_is_intensity(surf->base.format));
2630 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2635 surf->cb_dcc_control |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX11(tex->surface.u.gfx9.color.dcc.independent_128B_blocks);
2637 surf->cb_dcc_control |= S_028C78_INDEPENDENT_128B_BLOCKS_GFX10(tex->surface.u.gfx9.color.dcc.independent_128B_blocks);
2648 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2660 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2661 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2662 unsigned mip0_width = surf->width0 - 1;
2663 unsigned mip0_height = surf->height0 - 1;
2667 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2669 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2673 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2679 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(mip0_width) |
2684 surf->cb_color_view = color_view;
2685 surf->cb_color_info = color_info;
2686 surf->cb_color_attrib = color_attrib;
2689 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2691 surf->color_initialized = true;
2694 static void si_init_depth_surface(struct si_context *sctx, struct si_surface *surf)
2696 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2697 unsigned level = surf->base.u.tex.level;
2708 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2709 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2710 surf->db_htile_data_base = 0;
2711 surf->db_htile_surface = 0;
2714 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2715 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2720 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2721 surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.zs.stencil_offset) >> 8;
2732 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.epitch);
2733 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.zs.stencil_epitch);
2735 surf->db_depth_view |= S_028008_MIPID(level);
2736 surf->db_depth_size =
2750 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
2751 surf->db_htile_surface =
2754 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
2763 surf->db_depth_base =
2765 surf->db_stencil_base =
2771 surf->db_depth_info = 0;
2782 surf->db_depth_info |= S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2797 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2799 surf->db_depth_slice =
2822 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
2823 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2827 surf->db_z_info = z_info;
2828 surf->db_stencil_info = s_info;
2830 surf->depth_initialized = true;
2854 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2855 struct si_texture *tex = (struct si_texture *)surf->texture;
2857 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2860 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2868 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2869 struct si_texture *tex = (struct si_texture *)surf->texture;
2872 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2881 struct si_surface *surf = NULL;
2886 surf = (struct si_surface *)state->cbufs[i];
2887 tex = (struct si_texture *)surf->base.texture;
2923 struct si_surface *surf = NULL;
2950 surf = (struct si_surface *)state->cbufs[i];
2951 tex = (struct si_texture *)surf->base.texture;
2953 if (!surf->dcc_incompatible)
2956 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2960 surf->dcc_incompatible = false;
3043 surf = (struct si_surface *)state->cbufs[i];
3044 tex = (struct si_texture *)surf->base.texture;
3046 if (!surf->color_initialized) {
3047 si_initialize_color_surface(sctx, surf);
3051 sctx->framebuffer.spi_shader_col_format |= surf->spi_shader_col_format << (i * 4);
3052 sctx->framebuffer.spi_shader_col_format_alpha |= surf->spi_shader_col_format_alpha << (i * 4);
3053 sctx->framebuffer.spi_shader_col_format_blend |= surf->spi_shader_col_format_blend << (i * 4);
3054 sctx->framebuffer.spi_shader_col_format_blend_alpha |= surf->spi_shader_col_format_blend_alpha
3057 if (surf->color_is_int8)
3059 if (surf->color_is_int10)
3080 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3090 si_context_add_resource_size(sctx, surf->base.texture);
3103 surf = (struct si_surface *)state->zsbuf;
3104 zstex = (struct si_texture *)surf->base.texture;
3106 if (!surf->depth_initialized) {
3107 si_init_depth_surface(sctx, surf);
3110 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level, PIPE_MASK_ZS))
3113 si_context_add_resource_size(sctx, surf->base.texture);