Lines Matching defs:level
2667 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2673 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2697 unsigned level = surf->base.u.tex.level;
2735 surf->db_depth_view |= S_028008_MIPID(level);
2739 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2759 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2764 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.level[level].offset_256B;
2766 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.zs.stencil_level[level].offset_256B;
2775 unsigned index = tex->surface.u.legacy.tiling_index[level];
2776 unsigned stencil_index = tex->surface.u.legacy.zs.stencil_tiling_index[level];
2791 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2793 tile_mode_index = si_tile_mode_index(tex, level, true);
2802 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2857 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2860 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2872 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2956 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
3080 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3110 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level, PIPE_MASK_ZS))
3261 if (sctx->gfx_level < GFX11 && cb->base.u.tex.level > 0)
3270 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3300 S_028C78_FDCC_ENABLE(vi_dcc_enabled(tex, cb->base.u.tex.level));
3322 if (cb->base.u.tex.level > 0)
3369 if (cb->base.u.tex.level > 0)
3398 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3409 if (cb->base.u.tex.level > 0)
3412 cb_dcc_base += tex->surface.u.legacy.color.dcc_level[cb->base.u.tex.level].dcc_offset >> 8;
3416 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3472 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS);
3501 unsigned level = zb->base.u.tex.level;
3514 S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
3535 S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
3552 if (si_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS)) {
3572 S_028040_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
3583 radeon_emit(tex->stencil_clear_value[level]); /* R_028028_DB_STENCIL_CLEAR */
3584 radeon_emit(fui(tex->depth_clear_value[level])); /* R_02802C_DB_DEPTH_CLEAR */
4592 surflevel = tex->surface.u.legacy.level;