Lines Matching defs:info
87 (sctx->shader.ps.cso->info.colors_written & 0x3) != 0x3)
125 sctx->screen->info.has_dcc_constant_encode));
130 if (sctx->screen->info.rbplus_allowed) {
624 if (sctx->screen->info.rbplus_allowed) {
657 if (unlikely(sel->info.writes_1_if_tex_is_1 == 0xff)) {
672 sel->info.writes_1_if_tex_is_1 = 1 + texunit;
674 sel->info.writes_1_if_tex_is_1 = 0;
680 if (sel->info.writes_1_if_tex_is_1 &&
681 sel->info.writes_1_if_tex_is_1 != 0xff) {
683 int unit = sctx->shader.ps.cso->info.writes_1_if_tex_is_1 - 1;
701 const struct pipe_draw_info *info,
711 sctx->real_draw_vbo(ctx, info, drawid_offset, indirect, draws, num_draws);
717 struct pipe_draw_vertex_state_info info,
725 sctx->real_draw_vertex_state(ctx, state, partial_velem_mask, info, draws, num_draws);
745 if (sctx->screen->info.has_export_conflict_bug &&
852 struct si_shader_info *info = &vs_sel->info;
855 info->base.vs.window_space_position : 0;
856 unsigned clipdist_mask = vs_sel->info.clipdist_mask;
858 unsigned culldist_mask = vs_sel->info.culldist_mask;
1052 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.gfx_level >= GFX9));
1070 S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.gfx_level >= GFX10 ?
1155 if (sctx->screen->info.has_msaa_sample_loc_bug && sctx->framebuffer.nr_samples > 1)
1524 if (sctx->screen->info.has_dedicated_vram) {
1595 if (sctx->screen->info.has_rbplus && !sctx->screen->info.rbplus_allowed)
1598 if (sctx->screen->info.has_export_conflict_bug &&
1827 assert(sscreen->info.gfx_level <= GFX9);
1843 if (sscreen->info.gfx_level <= GFX8)
1897 (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA10 ||
1898 sscreen->info.family == CHIP_RAVEN || sscreen->info.family == CHIP_RAVEN2)) {
2093 if (!screen->info.has_3d_cube_border_color_mipmap) {
2177 sscreen->info.gfx_level == GFX9 &&
2218 if (sscreen->info.gfx_level >= GFX10) {
2219 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[format];
2235 assert(((struct si_screen *)screen)->info.gfx_level <= GFX9);
2309 assert(((struct si_screen *)screen)->info.gfx_level <= GFX9);
2369 if (sscreen->info.gfx_level >= GFX10) {
2370 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[format];
2415 !sscreen->info.has_3d_cube_border_color_mipmap)
2436 const unsigned max_eqaa_samples = util_bitcount(sscreen->info.enabled_rb_mask) <= 1 ? 8 : 16;
2443 if (!sscreen->info.has_eqaa_surface_allocator || util_format_is_depth_or_stencil(format)) {
2466 si_is_colorbuffer_format_supported(sscreen->info.gfx_level, format)) {
2626 if (!sctx->screen->info.has_dedicated_vram)
2774 struct radeon_info *info = &sctx->screen->info;
2778 unsigned tile_mode = info->si_tile_mode_array[index];
2779 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2780 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3489 if (sctx->screen->info.has_two_planes_iterate256_bug && iterate256 &&
3624 bool has_msaa_sample_loc_bug = sctx->screen->info.has_msaa_sample_loc_bug;
3708 if (sctx->shader.ps.cso && sctx->shader.ps.cso->info.base.writes_memory &&
3709 sctx->shader.ps.cso->info.base.fs.early_fragment_tests &&
3740 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3937 if (screen->info.gfx_level == GFX8)
3948 if (screen->info.gfx_level >= GFX10) {
3949 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&screen->info)[format];
3960 S_008F0C_RESOURCE_LEVEL(screen->info.gfx_level < GFX11);
4019 img_format = ac_get_gfx10_format_table(&screen->info)[pipe_format].img_format;
4049 if (screen->info.gfx_level >= GFX11) {
4082 S_00A008_RESOURCE_LEVEL(screen->info.gfx_level < GFX11);
4104 if (screen->info.gfx_level >= GFX11) {
4226 if (screen->info.gfx_level <= GFX8)
4312 if (screen->info.gfx_level == GFX9 && pipe_format == PIPE_FORMAT_S8_UINT)
4316 (screen->info.gfx_level <= GFX8 && res->target == PIPE_TEXTURE_3D))) {
4353 if (screen->info.gfx_level == GFX9) {
4379 if (screen->info.gfx_level <= GFX7 && res->nr_samples <= 1) {
4394 if (screen->info.gfx_level == GFX9) {
4500 if (screen->info.gfx_level == GFX9) {
4702 return (sctx->screen->info.gfx_level >= GFX11 ? S_008F3C_BORDER_COLOR_PTR_GFX11(i):
4756 (!sscreen->info.has_3d_cube_border_color_mipmap &&
4785 if (sscreen->info.gfx_level >= GFX10) {
4803 if (sscreen->info.gfx_level <= GFX9)
4860 struct util_fast_udiv_info info = util_compute_fast_udiv_info(D, num_bits, 32);
4863 info.multiplier,
4864 info.pre_shift,
4865 info.post_shift,
4866 info.increment,
4984 always_fix = sscreen->info.gfx_level <= GFX8 && sscreen->info.family != CHIP_STONEY &&
5029 (sscreen->info.gfx_level == GFX6 || sscreen->info.gfx_level >= GFX10);
5056 if (sscreen->info.gfx_level >= GFX10) {
5057 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(&sscreen->info)[elements[i].src_format];
5060 S_008F0C_RESOURCE_LEVEL(sscreen->info.gfx_level < GFX11);
5362 sctx->screen->info.tcc_rb_non_coherent)
5370 if (sctx->screen->info.gfx_level <= GFX7)
5385 if (sctx->screen->info.gfx_level <= GFX8 && flags & PIPE_BARRIER_INDIRECT_BUFFER)
5475 if (sscreen->info.gfx_level >= GFX10) {
5493 assert(se == ~0 || se < sctx->screen->info.max_se);
5503 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5507 ac_get_harvested_configs(&sctx->screen->info, raster_config, &raster_config_1, raster_config_se);
5523 unsigned num_rb = MIN2(sscreen->info.max_render_backends, 16);
5524 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5549 return u_bit_consecutive(0, sscreen->info.min_good_cu_per_sa);
5556 bool has_clear_state = sscreen->info.has_clear_state;
5659 C_00B01C_CU_EN, 0, &sscreen->info,
5679 if (sscreen->info.gfx_level >= GFX10) {
5681 S_00B524_MEM_BASE(sscreen->info.address32_hi >> 8));
5683 S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8));
5684 } else if (sscreen->info.gfx_level == GFX9) {
5686 S_00B414_MEM_BASE(sscreen->info.address32_hi >> 8));
5688 S_00B214_MEM_BASE(sscreen->info.address32_hi >> 8));
5691 S_00B524_MEM_BASE(sscreen->info.address32_hi >> 8));
5697 C_00B51C_CU_EN, 0, &sscreen->info, (void*)si_pm4_set_reg);
5701 C_00B31C_CU_EN, 0, &sscreen->info, (void*)si_pm4_set_reg);
5743 if (sscreen->info.gfx_level <= GFX9) {
5760 0, &sscreen->info,
5764 S_028C48_MAX_ALLOC_COUNT(sscreen->info.pbb_max_alloc_count - 1) |
5799 if (sscreen->info.max_render_backends <= 4) {
5856 sscreen->info.pa_sc_tile_steering_override);
5870 C_00B004_CU_EN, 16, &sscreen->info, (void*)si_pm4_set_reg_idx3);
5872 C_00B104_CU_EN, 16, &sscreen->info, (void*)si_pm4_set_reg_idx3);
5874 C_00B404_CU_EN, 16, &sscreen->info, (void*)si_pm4_set_reg_idx3);
5934 assert((sscreen->attribute_ring->gpu_address >> 32) == sscreen->info.address32_hi);
5941 sscreen->info.max_se) >> 16) - 1) |
5942 S_03111C_BIG_PAGE(sscreen->info.discardable_allows_big_page) |