Lines Matching defs:buffer
144 /* If the color buffer is not set, the driver sets 32_R
831 cb.buffer = NULL;
1306 * final stencil buffer result does not depend on the order of fragments. */
2167 unsigned res_target = tex->buffer.b.b.target;
2600 if (tex->buffer.b.b.nr_samples > 1) {
2601 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2602 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2641 if (tex->buffer.b.b.nr_storage_samples > 1) {
2664 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2681 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2706 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2720 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2721 surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.zs.stencil_offset) >> 8;
2723 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2725 S_028038_MAXMIP(tex->buffer.b.b.last_level) |
2737 S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) | S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2744 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2747 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2750 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
2764 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.level[level].offset_256B;
2766 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.zs.stencil_level[level].offset_256B;
2769 S_028040_FORMAT(format) | S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2809 * decompress messes with subsequent stencil buffer
2818 if (tex->buffer.b.b.nr_samples <= 1)
2822 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
2840 if (sctx->samplers[sh].views[i]->texture == &tex->buffer.b.b) {
2898 if (!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
2902 pipe_resource_reference(&dummy, &tex->buffer.b.b);
2981 * Only flush and wait for CB if there is actually a bound color buffer.
3070 if (tex->buffer.b.b.nr_samples >= 2 &&
3071 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
3073 MIN2(sctx->framebuffer.nr_color_samples, tex->buffer.b.b.nr_storage_samples);
3086 if (tex->buffer.b.b.nr_storage_samples >= 2)
3153 constbuf.buffer = sctx->sample_pos_buffer;
3230 sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC |
3231 (tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
3233 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3240 cb_color_base = tex->buffer.gpu_address >> 8;
3265 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
3281 cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
3461 /* ZS buffer. */
3469 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE |
3478 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM && tex->buffer.b.b.nr_samples > 1)
3482 bool iterate256 = tex->buffer.b.b.nr_samples >= 2;
3490 !tex->htile_stencil_disabled && tex->buffer.b.b.nr_samples == 4) {
3557 if (tex->buffer.b.b.nr_samples <= 1)
3559 else if (tex->buffer.b.b.nr_samples <= 4)
3897 * Build the sampler view descriptor for a buffer texture.
4011 struct pipe_resource *res = &tex->buffer.b.b;
4102 tex->buffer.b.b.last_level;
4122 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4197 struct pipe_resource *res = &tex->buffer.b.b;
4366 : tex->buffer.b.b.last_level);
4391 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4586 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4587 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
5017 * offset relative to the vertex buffer base is unaligned.
5020 * if the vertex buffer's offset is also unaligned in just the
5126 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
5164 struct pipe_resource *buf = src->buffer.resource;
5168 pipe_resource_reference(&dsti->buffer.resource, NULL);
5183 struct pipe_resource *buf = src->buffer.resource;
5186 pipe_resource_reference(&dsti->buffer.resource, buf);
5200 pipe_resource_reference(&dst[i].buffer.resource, NULL);
5204 pipe_resource_reference(&dst[count + i].buffer.resource, NULL);
5210 * shader changes. This check is conservative: a vertex buffer can only
5225 struct pipe_vertex_buffer *buffer,
5234 util_init_pipe_vertex_state(screen, buffer, elements, num_elements, indexbuf, full_velem_mask,
5249 assert(buffer->stride % 4 == 0);
5250 assert(buffer->buffer_offset % 4 == 0);
5251 assert(!buffer->is_user_buffer);
5275 struct pipe_vertex_buffer *buffer,
5283 return util_vertex_state_cache_get(screen, buffer, elements, num_elements, indexbuf,
5309 cb.buffer = NULL;
5338 /* This only ensures coherency for shader image/buffer stores. */