Lines Matching defs:sctx
61 static void si_query_sw_destroy(struct si_context *sctx, struct si_query *squery)
65 sctx->b.screen->fence_reference(sctx->b.screen, &query->fence, NULL);
119 static bool si_query_sw_begin(struct si_context *sctx, struct si_query *squery)
129 query->begin_result = sctx->num_draw_calls;
132 query->begin_result = sctx->num_decompress_calls;
135 query->begin_result = sctx->num_prim_restart_calls;
138 query->begin_result = sctx->num_compute_calls;
141 query->begin_result = sctx->num_cp_dma_calls;
144 query->begin_result = sctx->num_vs_flushes;
147 query->begin_result = sctx->num_ps_flushes;
150 query->begin_result = sctx->num_cs_flushes;
153 query->begin_result = sctx->num_cb_cache_flushes;
156 query->begin_result = sctx->num_db_cache_flushes;
159 query->begin_result = sctx->num_L2_invalidates;
162 query->begin_result = sctx->num_L2_writebacks;
165 query->begin_result = sctx->num_resident_handles;
168 query->begin_result = sctx->tc ? sctx->tc->num_offloaded_slots : 0;
171 query->begin_result = sctx->tc ? sctx->tc->num_direct_slots : 0;
174 query->begin_result = sctx->tc ? sctx->tc->num_syncs : 0;
199 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
204 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
205 query->begin_time = sctx->ws->query_value(sctx->ws, RADEON_NUM_GFX_IBS);
209 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
213 query->begin_result = sctx->tc ? util_queue_get_thread_time_nano(&sctx->tc->queue, 0) : 0;
237 query->begin_result = si_begin_counter(sctx->screen, query->b.type);
240 query->begin_result = p_atomic_read(&sctx->screen->num_compilations);
243 query->begin_result = p_atomic_read(&sctx->screen->num_shaders_created);
246 query->begin_result = sctx->screen->live_shader_cache.hits;
249 query->begin_result = sctx->screen->live_shader_cache.misses;
252 query->begin_result = sctx->screen->num_memory_shader_cache_hits;
255 query->begin_result = sctx->screen->num_memory_shader_cache_misses;
258 query->begin_result = sctx->screen->num_disk_shader_cache_hits;
261 query->begin_result = sctx->screen->num_disk_shader_cache_misses;
276 static bool si_query_sw_end(struct si_context *sctx, struct si_query *squery)
285 sctx->b.flush(&sctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
288 query->end_result = sctx->num_draw_calls;
291 query->end_result = sctx->num_decompress_calls;
294 query->end_result = sctx->num_prim_restart_calls;
297 query->end_result = sctx->num_compute_calls;
300 query->end_result = sctx->num_cp_dma_calls;
303 query->end_result = sctx->num_vs_flushes;
306 query->end_result = sctx->num_ps_flushes;
309 query->end_result = sctx->num_cs_flushes;
312 query->end_result = sctx->num_cb_cache_flushes;
315 query->end_result = sctx->num_db_cache_flushes;
318 query->end_result = sctx->num_L2_invalidates;
321 query->end_result = sctx->num_L2_writebacks;
324 query->end_result = sctx->num_resident_handles;
327 query->end_result = sctx->tc ? sctx->tc->num_offloaded_slots : 0;
330 query->end_result = sctx->tc ? sctx->tc->num_direct_slots : 0;
333 query->end_result = sctx->tc ? sctx->tc->num_syncs : 0;
355 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
360 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
361 query->end_time = sctx->ws->query_value(sctx->ws, RADEON_NUM_GFX_IBS);
365 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
369 query->end_result = sctx->tc ? util_queue_get_thread_time_nano(&sctx->tc->queue, 0) : 0;
393 query->end_result = si_end_counter(sctx->screen, query->b.type, query->begin_result);
397 query->end_result = p_atomic_read(&sctx->screen->num_compilations);
400 query->end_result = p_atomic_read(&sctx->screen->num_shaders_created);
403 query->end_result = sctx->last_tex_ps_draw_ratio;
406 query->end_result = sctx->screen->live_shader_cache.hits;
409 query->end_result = sctx->screen->live_shader_cache.misses;
412 query->end_result = sctx->screen->num_memory_shader_cache_hits;
415 query->end_result = sctx->screen->num_memory_shader_cache_misses;
418 query->end_result = sctx->screen->num_disk_shader_cache_hits;
421 query->end_result = sctx->screen->num_disk_shader_cache_misses;
436 static bool si_query_sw_get_result(struct si_context *sctx, struct si_query *squery, bool wait,
444 result->timestamp_disjoint.frequency = (uint64_t)sctx->screen->info.clock_crystal_freq * 1000;
448 struct pipe_screen *screen = sctx->b.screen;
449 struct pipe_context *ctx = squery->b.flushed ? NULL : &sctx->b;
468 result->u32 = sctx->screen->info.num_cu;
471 result->u32 = sctx->screen->info.max_render_backends;
477 result->u32 = sctx->screen->info.max_se;
532 void si_query_buffer_reset(struct si_context *sctx, struct si_query_buffer *buffer)
549 if (si_cs_is_buffer_referenced(sctx, buffer->buf->buf, RADEON_USAGE_READWRITE) ||
550 !sctx->ws->buffer_wait(sctx->ws, buffer->buf->buf, 0, RADEON_USAGE_READWRITE)) {
557 bool si_query_buffer_alloc(struct si_context *sctx, struct si_query_buffer *buffer,
576 struct si_screen *screen = sctx->screen;
585 if (unlikely(!prepare_buffer(sctx, buffer))) {
594 void si_query_hw_destroy(struct si_context *sctx, struct si_query *squery)
598 si_query_buffer_destroy(sctx->screen, &query->buffer);
603 static bool si_query_hw_prepare_buffer(struct si_context *sctx, struct si_query_buffer *qbuf)
606 struct si_screen *screen = sctx->screen;
609 uint32_t *results = screen->ws->buffer_map(sctx->ws, qbuf->buf->buf, NULL,
674 static void si_query_hw_get_result_resource(struct si_context *sctx, struct si_query *squery,
680 static void si_query_hw_do_emit_start(struct si_context *sctx, struct si_query_hw *query,
682 static void si_query_hw_do_emit_stop(struct si_context *sctx, struct si_query_hw *query,
756 static void si_update_occlusion_query_state(struct si_context *sctx, unsigned type, int diff)
760 bool old_enable = sctx->num_occlusion_queries != 0;
761 bool old_perfect_enable = sctx->num_perfect_occlusion_queries != 0;
764 sctx->num_occlusion_queries += diff;
765 assert(sctx->num_occlusion_queries >= 0);
768 sctx->num_perfect_occlusion_queries += diff;
769 assert(sctx->num_perfect_occlusion_queries >= 0);
772 enable = sctx->num_occlusion_queries != 0;
773 perfect_enable = sctx->num_perfect_occlusion_queries != 0;
776 si_set_occlusion_query_state(sctx, old_perfect_enable);
806 static void si_query_hw_do_emit_start(struct si_context *sctx, struct si_query_hw *query,
809 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
816 if (sctx->gfx_level >= GFX11) {
817 uint64_t rb_mask = BITFIELD64_MASK(sctx->screen->info.max_render_backends);
828 if (sctx->gfx_level >= GFX11)
848 si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
852 if (sctx->screen->use_ngg && query->flags & SI_QUERY_EMULATE_GS_COUNTERS) {
867 si_set_internal_shader_buffer(sctx, SI_GS_QUERY_EMULATED_COUNTERS_BUF, &sbuf);
868 SET_FIELD(sctx->current_gs_state, GS_STATE_PIPELINE_STATS_EMU, 1);
873 va += si_query_pipestat_end_dw_offset(sctx->screen, query->index) * 4;
881 sctx->num_pipeline_stat_emulated_queries++;
895 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf,
899 static void si_query_hw_emit_start(struct si_context *sctx, struct si_query_hw *query)
904 si_resource_reference(&query->buffer.buf, sctx->pipeline_stats_query_buf);
907 if ((!(query->flags & SI_QUERY_EMULATE_GS_COUNTERS) || !sctx->pipeline_stats_query_buf) &&
908 !si_query_buffer_alloc(sctx, &query->buffer, query->ops->prepare_buffer, query->result_size))
912 si_resource_reference(&sctx->pipeline_stats_query_buf, query->buffer.buf);
914 si_update_occlusion_query_state(sctx, query->b.type, 1);
915 si_update_prims_generated_query_state(sctx, query->b.type, 1);
918 sctx->num_pipeline_stat_queries++;
920 si_need_gfx_cs_space(sctx, 0);
923 query->ops->emit_start(sctx, query, query->buffer.buf, va);
926 static void si_query_hw_do_emit_stop(struct si_context *sctx, struct si_query_hw *query,
929 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
939 if (sctx->gfx_level >= GFX11)
947 fence_va = va + sctx->screen->info.max_render_backends * 16 - 8;
966 si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
976 if (sctx->screen->use_ngg && query->flags & SI_QUERY_EMULATE_GS_COUNTERS) {
980 if (--sctx->num_pipeline_stat_emulated_queries == 0) {
981 si_set_internal_shader_buffer(sctx, SI_GS_QUERY_BUF, NULL);
982 SET_FIELD(sctx->current_gs_state, GS_STATE_PIPELINE_STATS_EMU, 0);
998 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, query->buffer.buf,
1002 si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1008 static void si_query_hw_emit_stop(struct si_context *sctx, struct si_query_hw *query)
1014 si_need_gfx_cs_space(sctx, 0);
1015 if (!si_query_buffer_alloc(sctx, &query->buffer, query->ops->prepare_buffer,
1026 query->ops->emit_stop(sctx, query, query->buffer.buf, va);
1030 si_update_occlusion_query_state(sctx, query->b.type, -1);
1031 si_update_prims_generated_query_state(sctx, query->b.type, -1);
1034 sctx->num_pipeline_stat_queries--;
1212 struct si_context *sctx = (struct si_context *)ctx;
1215 squery->ops->destroy(sctx, squery);
1220 struct si_context *sctx = (struct si_context *)ctx;
1223 return squery->ops->begin(sctx, squery);
1226 bool si_query_hw_begin(struct si_context *sctx, struct si_query *squery)
1236 si_query_buffer_reset(sctx, &query->buffer);
1240 si_query_hw_emit_start(sctx, query);
1244 list_addtail(&query->b.active_list, &sctx->active_queries);
1245 sctx->num_cs_dw_queries_suspend += query->b.num_cs_dw_suspend;
1251 struct si_context *sctx = (struct si_context *)ctx;
1254 return squery->ops->end(sctx, squery);
1257 bool si_query_hw_end(struct si_context *sctx, struct si_query *squery)
1262 si_query_buffer_reset(sctx, &query->buffer);
1264 si_query_hw_emit_stop(sctx, query);
1268 sctx->num_cs_dw_queries_suspend -= query->b.num_cs_dw_suspend;
1277 static void si_get_hw_query_params(struct si_context *sctx, struct si_query_hw *squery, int index,
1280 unsigned max_rbs = sctx->screen->info.max_render_backends;
1336 params->end_offset = si_query_pipestat_end_dw_offset(sctx->screen, index) * 4;
1337 params->fence_offset = si_query_pipestats_num_results(sctx->screen) * 16;
1443 void si_query_hw_suspend(struct si_context *sctx, struct si_query *query)
1445 si_query_hw_emit_stop(sctx, (struct si_query_hw *)query);
1448 void si_query_hw_resume(struct si_context *sctx, struct si_query *query)
1450 si_query_hw_emit_start(sctx, (struct si_query_hw *)query);
1467 struct si_context *sctx = (struct si_context *)ctx;
1470 return squery->ops->get_result(sctx, squery, wait, result);
1477 struct si_context *sctx = (struct si_context *)ctx;
1480 squery->ops->get_result_resource(sctx, squery, flags, result_type, index, resource, offset);
1488 bool si_query_hw_get_result(struct si_context *sctx, struct si_query *squery, bool wait,
1491 struct si_screen *sscreen = sctx->screen;
1503 map = sctx->ws->buffer_map(sctx->ws, qbuf->buf->buf, NULL, usage);
1505 map = si_buffer_map(sctx, qbuf->buf, usage);
1524 static void si_query_hw_get_result_resource(struct si_context *sctx, struct si_query *squery,
1550 if (!sctx->query_result_shader) {
1551 sctx->query_result_shader = si_create_query_result_cs(sctx);
1552 if (!sctx->query_result_shader)
1557 u_suballocator_alloc(&sctx->allocator_zeroed_memory, 16, 16, &tmp_buffer_offset, &tmp_buffer);
1562 si_save_qbo_state(sctx, &saved_state);
1564 si_get_hw_query_params(sctx, query, index >= 0 ? index : 0, ¶ms);
1611 sctx->flags |= sctx->screen->barrier_flags.cp_to_L2;
1630 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, false, &constant_buffer);
1655 si_cp_wait_mem(sctx, &sctx->gfx_cs, va, 0x80000000, 0x80000000, WAIT_REG_MEM_EQUAL);
1657 si_launch_grid_internal_ssbos(sctx, &grid, sctx->query_result_shader,
1662 si_restore_qbo_state(sctx, &saved_state);
1669 struct si_context *sctx = (struct si_context *)ctx;
1671 struct si_atom *atom = &sctx->atoms.s.render_cond;
1680 if (((sctx->gfx_level == GFX8 && sctx->screen->info.pfp_fw_feature < 49) ||
1681 (sctx->gfx_level == GFX9 && sctx->screen->info.pfp_fw_feature < 38)) &&
1690 bool old_render_cond_enabled = sctx->render_cond_enabled;
1691 sctx->render_cond_enabled = false;
1693 u_suballocator_alloc(&sctx->allocator_zeroed_memory, 8, 8, &squery->workaround_offset,
1699 sctx->render_cond = NULL;
1706 sctx->flags |= sctx->screen->barrier_flags.L2_to_cp | SI_CONTEXT_FLUSH_FOR_RENDER_COND;
1708 sctx->render_cond_enabled = old_render_cond_enabled;
1712 sctx->render_cond = query;
1713 sctx->render_cond_invert = condition;
1714 sctx->render_cond_mode = mode;
1715 sctx->render_cond_enabled = query;
1717 si_set_atom_dirty(sctx, atom, query != NULL);
1720 void si_suspend_queries(struct si_context *sctx)
1724 LIST_FOR_EACH_ENTRY (query, &sctx->active_queries, active_list)
1725 query->ops->suspend(sctx, query);
1728 void si_resume_queries(struct si_context *sctx)
1733 si_need_gfx_cs_space(sctx, 0);
1735 LIST_FOR_EACH_ENTRY (query, &sctx->active_queries, active_list)
1736 query->ops->resume(sctx, query);
1937 void si_init_query_functions(struct si_context *sctx)
1939 sctx->b.create_query = si_create_query;
1940 sctx->b.create_batch_query = si_create_batch_query;
1941 sctx->b.destroy_query = si_destroy_query;
1942 sctx->b.begin_query = si_begin_query;
1943 sctx->b.end_query = si_end_query;
1944 sctx->b.get_query_result = si_get_query_result;
1945 sctx->b.get_query_result_resource = si_get_query_result_resource;
1947 if (sctx->has_graphics) {
1948 sctx->atoms.s.render_cond.emit = si_emit_query_predication;
1949 sctx->b.render_condition = si_render_condition;
1952 list_inithead(&sctx->active_queries);