Lines Matching refs:sctx
1299 void (*emit_spi_map[33])(struct si_context *sctx);
1325 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1326 void si_blitter_end(struct si_context *sctx);
1327 void si_init_blit_functions(struct si_context *sctx);
1328 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1336 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1337 void si_flush_implicit_resources(struct si_context *sctx);
1345 bool si_cs_is_buffer_referenced(struct si_context *sctx, struct pb_buffer *buf,
1347 void *si_buffer_map(struct si_context *sctx, struct si_resource *resource,
1364 void si_init_buffer_functions(struct si_context *sctx);
1382 bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsigned level,
1387 void si_execute_clears(struct si_context *sctx, struct si_clear_info *info,
1389 void si_init_clear_functions(struct si_context *sctx);
1404 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1406 void si_launch_grid_internal_ssbos(struct si_context *sctx, struct pipe_grid_info *info,
1415 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1419 void si_compute_clear_buffer_rmw(struct si_context *sctx, struct pipe_resource *dst,
1425 void si_copy_buffer(struct si_context *sctx, struct pipe_resource *dst, struct pipe_resource *src,
1427 bool si_compute_copy_image(struct si_context *sctx, struct pipe_resource *dst, unsigned dst_level,
1435 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1436 void gfx9_clear_dcc_msaa(struct si_context *sctx, struct pipe_resource *res, uint32_t clear_value,
1439 void si_init_compute_blit_functions(struct si_context *sctx);
1442 void si_cp_dma_wait_for_idle(struct si_context *sctx, struct radeon_cmdbuf *cs);
1443 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1447 void si_cp_dma_copy_buffer(struct si_context *sctx, struct pipe_resource *dst,
1451 void si_test_gds(struct si_context *sctx);
1452 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf, unsigned offset,
1454 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel,
1459 void si_init_cp_reg_shadowing(struct si_context *sctx);
1467 void si_log_hw_flush(struct si_context *sctx);
1468 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1469 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1470 void si_init_debug_functions(struct si_context *sctx);
1471 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved,
1474 void si_print_current_ib(struct si_context *sctx, FILE *f);
1499 void si_trace_emit(struct si_context *sctx);
1500 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
1502 void gfx10_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs);
1503 void si_emit_cache_flush(struct si_context *sctx, struct radeon_cmdbuf *cs);
1504 /* Replace the sctx->b.draw_vbo function with a wrapper. This can be use to implement
1507 void si_install_draw_wrapper(struct si_context *sctx, pipe_draw_vbo_func wrapper,
1516 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1517 void si_init_compute_functions(struct si_context *sctx);
1528 void si_inhibit_clockgating(struct si_context *sctx, struct radeon_cmdbuf *cs, bool inhibit);
1534 void si_emit_spm_setup(struct si_context *sctx, struct radeon_cmdbuf *cs);
1535 bool si_spm_init(struct si_context *sctx);
1536 void si_spm_finish(struct si_context *sctx);
1540 void si_init_query_functions(struct si_context *sctx);
1541 void si_suspend_queries(struct si_context *sctx);
1542 void si_resume_queries(struct si_context *sctx);
1545 void *si_create_copy_image_cs(struct si_context *sctx, bool src_is_1d_array, bool dst_is_1d_array);
1546 void *si_create_dcc_retile_cs(struct si_context *sctx, struct radeon_surf *surf);
1547 void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *tex);
1548 void *si_create_passthrough_tcs(struct si_context *sctx);
1551 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1555 void *si_create_clear_buffer_rmw_cs(struct si_context *sctx);
1560 void *si_create_query_result_cs(struct si_context *sctx);
1561 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1564 void gfx10_init_query(struct si_context *sctx);
1565 void gfx10_destroy_query(struct si_context *sctx);
1590 void si_eliminate_fast_color_clear(struct si_context *sctx, struct si_texture *tex,
1604 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx, struct pipe_resource *tex,
1608 bool si_texture_disable_dcc(struct si_context *sctx, struct si_texture *tex);
1610 void si_init_context_texture_functions(struct si_context *sctx);
1613 void si_sqtt_write_event_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1618 bool si_sqtt_register_pipeline(struct si_context* sctx, uint64_t pipeline_hash, uint64_t base_address, bool is_compute);
1621 void si_sqtt_describe_pipeline_bind(struct si_context* sctx, uint64_t pipeline_hash, int bind_point);
1623 si_write_event_with_dims_marker(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1627 si_write_user_event(struct si_context* sctx, struct radeon_cmdbuf *rcs,
1631 si_sqtt_describe_barrier_start(struct si_context* sctx, struct radeon_cmdbuf *rcs);
1633 si_sqtt_describe_barrier_end(struct si_context* sctx, struct radeon_cmdbuf *rcs, unsigned flags);
1634 bool si_init_thread_trace(struct si_context *sctx);
1635 void si_destroy_thread_trace(struct si_context *sctx);
1636 void si_handle_thread_trace(struct si_context *sctx, struct radeon_cmdbuf *rcs);
1658 si_shader_selector_reference(struct si_context *sctx, /* sctx can optionally be NULL */
1665 util_shader_reference(&sctx->b, &sscreen->live_shader_cache, (void **)dst, src);
1681 static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx,
1689 return 2048 + sctx->num_cs_dw_queries_suspend + num_draws * 10;
1692 static inline void si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1696 sctx->memory_usage_kb += si_resource(r)->memory_usage_kb;
1700 static inline void si_invalidate_draw_sh_constants(struct si_context *sctx)
1702 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1703 sctx->last_start_instance = SI_START_INSTANCE_UNKNOWN;
1704 sctx->last_drawid = SI_DRAW_ID_UNKNOWN;
1707 static inline void si_invalidate_draw_constants(struct si_context *sctx)
1709 si_invalidate_draw_sh_constants(sctx);
1710 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1713 static inline unsigned si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1715 return 1 << (atom - sctx->atoms.array);
1718 static inline void si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1720 unsigned bit = si_get_atom_bit(sctx, atom);
1723 sctx->dirty_atoms |= bit;
1725 sctx->dirty_atoms &= ~bit;
1728 static inline bool si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1730 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1733 static inline void si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1735 si_set_atom_dirty(sctx, atom, true);
1738 /* This should be evaluated at compile time if all parameters except sctx are constants. */
1740 si_get_vs_inline(struct si_context *sctx, enum si_has_tess has_tess, enum si_has_gs has_gs)
1743 return &sctx->shader.gs;
1745 return &sctx->shader.tes;
1747 return &sctx->shader.vs;
1750 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1752 return si_get_vs_inline(sctx, sctx->shader.tes.cso ? TESS_ON : TESS_OFF,
1753 sctx->shader.gs.cso ? GS_ON : GS_OFF);
1761 static inline bool si_get_strmout_en(struct si_context *sctx)
1763 return sctx->streamout.streamout_enabled || sctx->streamout.prims_gen_query_enabled;
1766 static inline unsigned si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1776 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1788 static inline void si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1791 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_INV_VCACHE;
1792 sctx->force_cb_shader_coherent = false;
1794 if (sctx->gfx_level >= GFX10) {
1795 if (sctx->screen->info.tcc_rb_non_coherent)
1796 sctx->flags |= SI_CONTEXT_INV_L2;
1798 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1799 } else if (sctx->gfx_level == GFX9) {
1805 sctx->flags |= SI_CONTEXT_INV_L2;
1807 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1810 sctx->flags |= SI_CONTEXT_INV_L2;
1814 static inline void si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1817 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB | SI_CONTEXT_INV_VCACHE;
1819 if (sctx->gfx_level >= GFX10) {
1820 if (sctx->screen->info.tcc_rb_non_coherent)
1821 sctx->flags |= SI_CONTEXT_INV_L2;
1823 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1824 } else if (sctx->gfx_level == GFX9) {
1830 sctx->flags |= SI_CONTEXT_INV_L2;
1832 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1835 sctx->flags |= SI_CONTEXT_INV_L2;
1871 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1873 if (sctx->ps_uses_fbfetch)
1874 return sctx->framebuffer.nr_color_samples;
1876 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1879 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1881 if (sctx->queued.named.rasterizer->rasterizer_discard)
1884 struct si_shader_selector *ps = sctx->shader.ps.cso;
1889 sctx->framebuffer.colorbuf_enabled_4bit & sctx->queued.named.blend->cb_target_mask;
1970 static inline void radeon_add_to_buffer_list(struct si_context *sctx, struct radeon_cmdbuf *cs,
1974 sctx->ws->cs_add_buffer(cs, bo->buf, usage | RADEON_USAGE_SYNCHRONIZED,
1993 static inline void radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1999 !radeon_cs_memory_below_limit(sctx->screen, &sctx->gfx_cs, sctx->memory_usage_kb + bo->memory_usage_kb))
2000 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2002 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, bo, usage);
2005 static inline void si_select_draw_vbo(struct si_context *sctx)
2007 pipe_draw_vbo_func draw_vbo = sctx->draw_vbo[!!sctx->shader.tes.cso]
2008 [!!sctx->shader.gs.cso]
2009 [sctx->ngg];
2011 sctx->draw_vertex_state[!!sctx->shader.tes.cso]
2012 [!!sctx->shader.gs.cso]
2013 [sctx->ngg];
2017 if (unlikely(sctx->real_draw_vbo)) {
2018 assert(sctx->real_draw_vertex_state);
2019 sctx->real_draw_vbo = draw_vbo;
2020 sctx->real_draw_vertex_state = draw_vertex_state;
2022 assert(!sctx->real_draw_vertex_state);
2023 sctx->b.draw_vbo = draw_vbo;
2024 sctx->b.draw_vertex_state = draw_vertex_state;
2029 static inline unsigned si_get_num_coverage_samples(struct si_context *sctx)
2031 if (sctx->framebuffer.nr_samples > 1 &&
2032 sctx->queued.named.rasterizer->multisample_enable)
2033 return sctx->framebuffer.nr_samples;
2036 if (sctx->smoothing_enabled)
2057 void si_check_dirty_buffers_textures(struct si_context *sctx)
2060 unsigned dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
2061 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
2062 sctx->last_dirty_tex_counter = dirty_tex_counter;
2063 sctx->framebuffer.dirty_cbufs |= ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
2064 sctx->framebuffer.dirty_zsbuf = true;
2065 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2066 si_update_all_texture_descriptors(sctx);
2069 unsigned dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
2070 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
2071 sctx->last_dirty_buf_counter = dirty_buf_counter;
2073 si_rebind_buffer(sctx, NULL);