Lines Matching refs:screen
558 void (*make_texture_descriptor)(struct si_screen *screen, struct si_texture *tex, bool sampler,
610 /* This must be in the screen, because UE4 uses one context for
670 * - The shader cache is per screen (= per process), never saved to
987 struct si_screen *screen;
1352 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1354 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen, unsigned flags,
1356 struct pipe_resource *si_buffer_from_winsys_buffer(struct pipe_screen *screen,
1481 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1485 void si_init_screen_fence_functions(struct si_screen *screen);
1526 void si_init_perfcounters(struct si_screen *screen);
1527 void si_destroy_perfcounters(struct si_screen *screen);
1596 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1664 struct si_screen *sscreen = src ? src->screen : (*dst)->screen;
1776 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1795 if (sctx->screen->info.tcc_rb_non_coherent)
1820 if (sctx->screen->info.tcc_rb_non_coherent)
1852 struct si_screen *sscreen = (struct si_screen *)tex->buffer.b.b.screen;
1936 static inline bool radeon_cs_memory_below_limit(struct si_screen *screen, struct radeon_cmdbuf *cs,
1939 return kb + cs->used_vram_kb + cs->used_gart_kb < screen->max_memory_usage_kb;
1953 if (radeon_cs_memory_below_limit(ctx->screen, &ctx->gfx_cs, kb) &&
1999 !radeon_cs_memory_below_limit(sctx->screen, &sctx->gfx_cs, sctx->memory_usage_kb + bo->memory_usage_kb))
2060 unsigned dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
2069 unsigned dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);