Lines Matching refs:sscreen
139 bool si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler)
144 !sscreen->info.has_dedicated_vram && sscreen->info.gfx_level <= GFX8;
147 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
152 if (!ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options))
162 void si_init_aux_async_compute_ctx(struct si_screen *sscreen)
164 assert(!sscreen->async_compute_context);
165 sscreen->async_compute_context = si_create_context(
166 &sscreen->b,
168 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
172 if (sscreen->async_compute_context)
173 ((struct si_context*)sscreen->async_compute_context)->cs_max_waves_per_sh = 2;
458 struct si_screen *sscreen = (struct si_screen *)screen;
462 if (!sscreen->info.has_graphics && !(flags & PIPE_CONTEXT_COMPUTE_ONLY)) {
468 struct radeon_winsys *ws = sscreen->ws;
478 sctx->has_graphics = sscreen->info.gfx_level == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
481 sscreen->record_llvm_ir = true; /* racy but not critical */
486 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
490 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
491 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
493 sctx->ws = sscreen->ws;
494 sctx->family = sscreen->info.family;
495 sctx->gfx_level = sscreen->info.gfx_level;
499 &sscreen->b, PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
500 PIPE_USAGE_DEFAULT, 16 * sscreen->info.max_render_backends, 256);
551 bool smart_access_memory = sscreen->info.smart_access_memory;
552 bool is_apu = !sscreen->info.has_dedicated_vram;
575 if (sscreen->info.has_3d_cube_border_color_mipmap) {
597 sctx->ngg = sscreen->use_ngg;
687 if (sscreen->info.ip[AMD_IP_UVD].num_queues || sscreen->info.has_video_hw.vcn_decode ||
688 sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues || sscreen->info.ip[AMD_IP_VCE].num_queues ||
689 sscreen->info.ip[AMD_IP_UVD_ENC].num_queues || sscreen->info.ip[AMD_IP_VCN_ENC].num_queues) {
777 sscreen->info.tcc_cache_line_size);
802 struct si_context *saux = si_get_aux_context(sscreen);
813 &sscreen->b, SI_CONTEXT_FLAG_AUX |
814 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
815 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
817 sscreen->aux_context = saux;
819 si_put_aux_context_flush(sscreen);
821 simple_mtx_lock(&sscreen->async_compute_context_lock);
822 if (status != PIPE_NO_RESET && sscreen->async_compute_context) {
823 sscreen->async_compute_context->destroy(sscreen->async_compute_context);
824 sscreen->async_compute_context = NULL;
826 simple_mtx_unlock(&sscreen->async_compute_context_lock);
852 struct si_screen *sscreen = (struct si_screen *)screen;
855 if (sscreen->debug_flags & DBG(CHECK_VM))
860 if (ctx && sscreen->info.gfx_level >= GFX9 && sscreen->debug_flags & DBG(SQTT)) {
861 if (ac_check_profile_state(&sscreen->info)) {
881 if (sscreen->debug_flags & DBG_ALL_SHADERS)
887 threaded_context_create(ctx, &sscreen->pool_transfers,
890 .create_fence = sscreen->info.is_amdgpu ?
908 struct si_screen *sscreen = (struct si_screen *)pscreen;
909 struct si_shader_part *parts[] = {sscreen->vs_prologs, sscreen->tcs_epilogs,
910 sscreen->ps_prologs, sscreen->ps_epilogs};
913 if (!sscreen->ws->unref(sscreen->ws))
916 if (sscreen->debug_flags & DBG(CACHE_STATS)) {
917 printf("live shader cache: hits = %u, misses = %u\n", sscreen->live_shader_cache.hits,
918 sscreen->live_shader_cache.misses);
919 printf("memory shader cache: hits = %u, misses = %u\n", sscreen->num_memory_shader_cache_hits,
920 sscreen->num_memory_shader_cache_misses);
921 printf("disk shader cache: hits = %u, misses = %u\n", sscreen->num_disk_shader_cache_hits,
922 sscreen->num_disk_shader_cache_misses);
925 si_resource_reference(&sscreen->attribute_ring, NULL);
927 if (sscreen->aux_context) {
928 struct si_context *saux = si_get_aux_context(sscreen);
937 mtx_unlock(&sscreen->aux_context_lock);
939 mtx_destroy(&sscreen->aux_context_lock);
941 simple_mtx_destroy(&sscreen->async_compute_context_lock);
942 if (sscreen->async_compute_context) {
943 sscreen->async_compute_context->destroy(sscreen->async_compute_context);
946 util_queue_destroy(&sscreen->shader_compiler_queue);
947 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
952 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
953 si_destroy_compiler(&sscreen->compiler[i]);
955 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
956 si_destroy_compiler(&sscreen->compiler_lowp[i]);
968 simple_mtx_destroy(&sscreen->shader_parts_mutex);
969 si_destroy_shader_cache(sscreen);
971 si_destroy_perfcounters(sscreen);
972 si_gpu_load_kill_thread(sscreen);
974 simple_mtx_destroy(&sscreen->gpu_load_mutex);
975 simple_mtx_destroy(&sscreen->gds_mutex);
977 radeon_bo_reference(sscreen->ws, &sscreen->gds, NULL);
978 radeon_bo_reference(sscreen->ws, &sscreen->gds_oa, NULL);
980 slab_destroy_parent(&sscreen->pool_transfers);
982 disk_cache_destroy(sscreen->disk_shader_cache);
983 util_live_shader_cache_deinit(&sscreen->live_shader_cache);
984 util_idalloc_mt_fini(&sscreen->buffer_ids);
985 util_vertex_state_cache_deinit(&sscreen->vertex_state_cache);
987 sscreen->ws->destroy(sscreen->ws);
988 FREE(sscreen);
991 static void si_init_gs_info(struct si_screen *sscreen)
993 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.gfx_level, sscreen->info.family);
996 static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags)
998 struct pipe_context *ctx = sscreen->aux_context;
1000 struct pipe_resource *buf = pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
1054 static void si_disk_cache_create(struct si_screen *sscreen)
1057 if (sscreen->debug_flags & DBG_ALL_SHADERS)
1073 sscreen->disk_shader_cache = disk_cache_create(sscreen->info.name, cache_id,
1074 sscreen->info.address32_hi);
1079 struct si_screen *sscreen = (struct si_screen *)screen;
1083 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue, max_threads);
1098 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
1102 if (!sscreen) {
1108 sscreen->options.name = driQueryOptionb(config->options, "radeonsi_" #name);
1110 sscreen->options.name = driQueryOptioni(config->options, "radeonsi_" #name);
1114 sscreen->ws = ws;
1115 ws->query_info(ws, &sscreen->info,
1116 sscreen->options.enable_sam,
1117 sscreen->options.disable_sam);
1119 if (sscreen->info.gfx_level >= GFX9) {
1120 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
1122 ac_get_raster_config(&sscreen->info, &sscreen->pa_sc_raster_config,
1123 &sscreen->pa_sc_raster_config_1, &sscreen->se_tile_repeat);
1126 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", radeonsi_debug_options, 0);
1127 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", radeonsi_debug_options, 0);
1130 if (sscreen->debug_flags & DBG(NO_GFX))
1131 sscreen->info.has_graphics = false;
1133 if ((sscreen->debug_flags & DBG(TMZ)) &&
1134 !sscreen->info.has_tmz_support) {
1136 FREE(sscreen);
1143 if (!si_init_compiler(sscreen, &sscreen->compiler[0])) {
1145 FREE(sscreen);
1149 util_idalloc_mt_init_tc(&sscreen->buffer_ids);
1152 sscreen->b.context_create = si_pipe_create_context;
1153 sscreen->b.destroy = si_destroy_screen;
1154 sscreen->b.set_max_shader_compiler_threads = si_set_max_shader_compiler_threads;
1155 sscreen->b.is_parallel_shader_compilation_finished = si_is_parallel_shader_compilation_finished;
1156 sscreen->b.finalize_nir = si_finalize_nir;
1158 si_init_screen_get_functions(sscreen);
1159 si_init_screen_buffer_functions(sscreen);
1160 si_init_screen_fence_functions(sscreen);
1161 si_init_screen_state_functions(sscreen);
1162 si_init_screen_texture_functions(sscreen);
1163 si_init_screen_query_functions(sscreen);
1164 si_init_screen_live_shader_cache(sscreen);
1166 sscreen->max_texel_buffer_elements = sscreen->b.get_param(
1167 &sscreen->b, PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT);
1177 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1179 if (sscreen->debug_flags & DBG(INFO))
1180 ac_print_gpu_info(&sscreen->info, stdout);
1182 slab_create_parent(&sscreen->pool_transfers, sizeof(struct si_transfer), 64);
1184 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1185 if (sscreen->force_aniso == -1) {
1186 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1189 if (sscreen->force_aniso >= 0) {
1192 1 << util_logbase2(sscreen->force_aniso));
1195 (void)mtx_init(&sscreen->aux_context_lock, mtx_recursive);
1196 (void)simple_mtx_init(&sscreen->async_compute_context_lock, mtx_plain);
1197 (void)simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
1198 (void)simple_mtx_init(&sscreen->gds_mutex, mtx_plain);
1200 si_init_gs_info(sscreen);
1201 if (!si_init_shader_cache(sscreen)) {
1202 FREE(sscreen);
1206 if (sscreen->info.gfx_level < GFX10_3)
1207 sscreen->options.vrs2x2 = false;
1209 si_disk_cache_create(sscreen);
1241 num_comp_hi_threads = MIN2(num_comp_hi_threads, ARRAY_SIZE(sscreen->compiler));
1242 num_comp_lo_threads = MIN2(num_comp_lo_threads, ARRAY_SIZE(sscreen->compiler_lowp));
1252 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh", num_slots,
1257 si_destroy_shader_cache(sscreen);
1258 FREE(sscreen);
1263 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority, "shlo", num_slots,
1269 si_destroy_shader_cache(sscreen);
1270 FREE(sscreen);
1276 si_init_perfcounters(sscreen);
1278 sscreen->max_memory_usage_kb = sscreen->info.vram_size_kb + sscreen->info.gart_size_kb / 4 * 3;
1280 ac_get_hs_info(&sscreen->info, &sscreen->hs);
1282 sscreen->has_draw_indirect_multi =
1283 (sscreen->info.family >= CHIP_POLARIS10) ||
1284 (sscreen->info.gfx_level == GFX8 && sscreen->info.pfp_fw_version >= 121 &&
1285 sscreen->info.me_fw_version >= 87) ||
1286 (sscreen->info.gfx_level == GFX7 && sscreen->info.pfp_fw_version >= 211 &&
1287 sscreen->info.me_fw_version >= 173) ||
1288 (sscreen->info.gfx_level == GFX6 && sscreen->info.pfp_fw_version >= 79 &&
1289 sscreen->info.me_fw_version >= 142);
1291 sscreen->has_out_of_order_rast =
1292 sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1294 if (sscreen->info.gfx_level >= GFX11) {
1295 sscreen->use_ngg = true;
1296 sscreen->use_ngg_streamout = true;
1298 sscreen->use_ngg_culling = (sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_ALL)) &&
1299 !(sscreen->debug_flags & DBG(NO_NGG_CULLING));
1301 sscreen->use_ngg = !(sscreen->debug_flags & DBG(NO_NGG)) &&
1302 sscreen->info.gfx_level >= GFX10 &&
1303 (sscreen->info.family != CHIP_NAVI14 ||
1304 sscreen->info.is_pro_graphics);
1305 sscreen->use_ngg_streamout = false;
1306 sscreen->use_ngg_culling = sscreen->use_ngg &&
1307 sscreen->info.max_render_backends >= 2 &&
1308 !(sscreen->debug_flags & DBG(NO_NGG_CULLING)) &&
1315 if (sscreen->info.gfx_level >= GFX10) {
1316 memset(sscreen->allow_dcc_msaa_clear_to_reg_for_bpp, true,
1317 sizeof(sscreen->allow_dcc_msaa_clear_to_reg_for_bpp));
1318 } else if (sscreen->info.gfx_level == GFX9) {
1320 sscreen->allow_dcc_msaa_clear_to_reg_for_bpp[bpp_log2] = true;
1326 sscreen->always_allow_dcc_stores = !(sscreen->debug_flags & DBG(NO_DCC_STORE)) &&
1327 (sscreen->debug_flags & DBG(DCC_STORE) ||
1328 sscreen->info.gfx_level >= GFX11 || /* always enabled on gfx11 */
1329 (sscreen->info.gfx_level >= GFX10_3 &&
1330 !sscreen->info.has_dedicated_vram));
1332 sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB)) &&
1333 (sscreen->info.gfx_level >= GFX10 ||
1335 (sscreen->info.gfx_level == GFX9 && !sscreen->info.has_dedicated_vram) ||
1336 sscreen->debug_flags & DBG(DPBB));
1338 if (sscreen->dpbb_allowed) {
1339 if (sscreen->info.has_dedicated_vram) {
1340 if (sscreen->info.max_render_backends > 4) {
1341 sscreen->pbb_context_states_per_bin = 1;
1342 sscreen->pbb_persistent_states_per_bin = 1;
1344 sscreen->pbb_context_states_per_bin = 3;
1345 sscreen->pbb_persistent_states_per_bin = 8;
1352 sscreen->pbb_context_states_per_bin = sscreen->info.has_gfx9_scissor_bug ? 1 : 6;
1354 sscreen->pbb_persistent_states_per_bin = 16;
1357 assert(sscreen->pbb_context_states_per_bin >= 1 &&
1358 sscreen->pbb_context_states_per_bin <= 6);
1359 assert(sscreen->pbb_persistent_states_per_bin >= 1 &&
1360 sscreen->pbb_persistent_states_per_bin <= 32);
1363 (void)simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1364 sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1366 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
1367 if (sscreen->info.gfx_level <= GFX8) {
1368 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1369 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1373 sscreen->debug_flags |= DBG_ALL_SHADERS;
1389 if (sscreen->info.has_eqaa_surface_allocator) {
1394 sscreen->eqaa_force_coverage_samples = s;
1395 sscreen->eqaa_force_z_samples = z;
1396 sscreen->eqaa_force_color_samples = f;
1400 sscreen->ngg_subgroup_size = 128;
1402 if (sscreen->info.gfx_level >= GFX11) {
1405 unsigned attr_ring_size = attr_ring_size_per_se * sscreen->info.max_se;
1407 sscreen->attribute_ring = si_aligned_buffer_create(&sscreen->b,
1417 sscreen->aux_context = si_create_context(
1418 &sscreen->b,
1420 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1421 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1423 if (sscreen->options.aux_debug) {
1426 si_get_aux_context(sscreen)->b.set_log_context(sscreen->aux_context, log);
1427 si_put_aux_context_flush(sscreen);
1431 si_test_image_copy_region(sscreen);
1434 si_test_blit(sscreen, test_flags);
1437 si_test_dma_perf(sscreen);
1441 si_test_vmfault(sscreen, test_flags);
1444 si_test_gds((struct si_context *)sscreen->aux_context);
1447 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 32 * 1024, 4,
1451 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 4, 1,
1455 ac_print_shadowed_regs(&sscreen->info);
1458 return &sscreen->b;
1482 struct si_context* si_get_aux_context(struct si_screen *sscreen)
1484 mtx_lock(&sscreen->aux_context_lock);
1485 return (struct si_context*)sscreen->aux_context;
1488 void si_put_aux_context_flush(struct si_screen *sscreen)
1490 struct pipe_context *c = &((struct si_context*)sscreen->aux_context)->b;
1492 mtx_unlock(&sscreen->aux_context_lock);