Lines Matching defs:value
64 unsigned value = S_030800_SH_BROADCAST_WRITES(1);
67 value |= S_030800_SE_INDEX(se);
69 value |= S_030800_SE_BROADCAST_WRITES(1);
74 value |= S_030800_SA_BROADCAST_WRITES(1);
78 value |= S_030800_INSTANCE_INDEX(instance);
80 value |= S_030800_INSTANCE_BROADCAST_WRITES(1);
84 radeon_set_uconfig_reg(R_030800_GRBM_GFX_INDEX, value);
403 uint32_t value = results[counter->base + j * counter->stride];
404 result->batch[i].u64 += value;
490 // A non-zero value in query->shaders ensures that the shader