Lines Matching refs:sscreen
49 struct si_screen *sscreen = (struct si_screen *)pscreen;
52 bool enable_sparse = sscreen->info.gfx_level >= GFX9 &&
53 sscreen->info.has_sparse_vm_mappings;
177 return !(sscreen->debug_flags & DBG(NO_FAST_DISPLAY_LIST));
180 return sscreen->info.gfx_level < GFX11;
189 return sscreen->info.has_3d_cube_border_color_mipmap;
192 return sscreen->info.gfx_level >= GFX10;
195 return sscreen->info.has_graphics;
198 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
201 return sscreen->info.has_tmz_support;
238 if (sscreen->info.gfx_level <= GFX8)
253 unsigned max_size = MIN2((sscreen->info.max_heap_size_kb * 1024ull) / 4, UINT32_MAX);
264 return sscreen->info.max_heap_size_kb / 1024 / 4;
280 if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 22))
287 return sscreen->info.has_syncobj;
293 return sscreen->info.has_fence_to_handle;
298 return sscreen->has_draw_indirect_multi;
307 return sscreen->info.gfx_level <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
333 if (!sscreen->info.has_3d_cube_border_color_mipmap)
337 if (!sscreen->info.has_3d_cube_border_color_mipmap)
339 if (sscreen->info.gfx_level >= GFX10)
344 if (sscreen->info.gfx_level >= GFX10)
372 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
388 return sscreen->info.pci_id;
390 return sscreen->info.vram_size_kb >> 10;
392 return sscreen->info.pci_domain;
394 return sscreen->info.pci_bus;
396 return sscreen->info.pci_dev;
398 return sscreen->info.pci_func;
439 struct si_screen *sscreen = (struct si_screen *)pscreen;
501 return sscreen->info.gfx_level >= GFX8 && sscreen->options.fp16;
516 struct si_screen *sscreen = (struct si_screen *)screen;
519 return &sscreen->nir_options;
529 struct si_screen *sscreen = (struct si_screen *)pscreen;
531 ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
536 struct si_screen *sscreen = (struct si_screen *)pscreen;
538 return sscreen->renderer_string;
571 struct si_screen *sscreen = (struct si_screen *)screen;
575 if (!(sscreen->info.ip[AMD_IP_VCE].num_queues ||
576 sscreen->info.ip[AMD_IP_UVD_ENC].num_queues ||
577 sscreen->info.ip[AMD_IP_VCN_ENC].num_queues))
584 (sscreen->info.family >= CHIP_RAVEN || si_vce_is_fw_version_supported(sscreen))) ||
586 (sscreen->info.family >= CHIP_RAVEN || si_radeon_uvd_enc_supported(sscreen))) ||
587 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.family >= CHIP_RENOIR));
592 sscreen->info.enc_caps.codec_info[codec - 1].valid)
593 return sscreen->info.enc_caps.codec_info[codec - 1].max_width;
595 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
598 sscreen->info.enc_caps.codec_info[codec - 1].valid)
599 return sscreen->info.enc_caps.codec_info[codec - 1].max_height;
601 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
614 return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
617 sscreen->info.family >= CHIP_RAVEN)
629 sscreen->info.family >= CHIP_NAVI24)
632 !(sscreen->info.ip[AMD_IP_UVD].num_queues ||
633 sscreen->info.has_video_hw.vcn_decode))
638 if (sscreen->info.gfx_level >= GFX11)
643 if (sscreen->info.gfx_level >= GFX11)
648 if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
649 sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
655 if (sscreen->info.gfx_level >= GFX11)
661 if (sscreen->info.family >= CHIP_STONEY)
664 else if (sscreen->info.family >= CHIP_CARRIZO)
668 if (sscreen->info.family >= CHIP_RAVEN) {
669 if (!sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues)
674 if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
676 if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
682 if (sscreen->info.family < CHIP_RAVEN)
686 if (sscreen->info.family < CHIP_NAVI21)
696 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
697 return sscreen->info.dec_caps.codec_info[codec - 1].max_width;
703 return (sscreen->info.family < CHIP_RENOIR) ?
704 ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) : 8192;
706 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
711 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
712 return sscreen->info.dec_caps.codec_info[codec - 1].max_height;
718 return (sscreen->info.family < CHIP_RENOIR) ?
719 ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) : 4352;
721 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
747 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
748 return sscreen->info.dec_caps.codec_info[codec - 1].max_level;
769 return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
814 struct si_screen *sscreen = (struct si_screen *)screen;
822 gpu = ac_get_llvm_processor_name(sscreen->info.family);
848 unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
858 *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
883 MIN2(4 * max_mem_alloc_size, sscreen->info.max_heap_size_kb * 1024ull);
891 if (sscreen->info.gfx_level == GFX6)
913 *max_mem_alloc_size = (sscreen->info.max_heap_size_kb / 4) * 1024ull;
920 *max_clock_frequency = sscreen->info.max_gpu_freq_mhz;
927 *max_compute_units = sscreen->info.num_cu;
942 *subgroup_size = si_determine_wave_size(sscreen, NULL);
962 struct si_screen *sscreen = (struct si_screen *)screen;
964 return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
965 sscreen->info.clock_crystal_freq;
970 struct si_screen *sscreen = (struct si_screen *)screen;
971 struct radeon_winsys *ws = sscreen->ws;
974 info->total_device_memory = sscreen->info.vram_size_kb;
975 info->total_staging_memory = sscreen->info.gart_size_kb;
997 if (sscreen->info.is_amdgpu)
1006 struct si_screen *sscreen = (struct si_screen *)pscreen;
1008 return sscreen->disk_shader_cache;
1011 static void si_init_renderer_string(struct si_screen *sscreen)
1017 sscreen->info.marketing_name ? sscreen->info.marketing_name : sscreen->info.name);
1018 snprintf(second_name, sizeof(second_name), "%s, ", sscreen->info.lowercase_name);
1023 snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
1025 sscreen->info.drm_major, sscreen->info.drm_minor, kernel_version);
1028 void si_init_screen_get_functions(struct si_screen *sscreen)
1030 sscreen->b.get_name = si_get_name;
1031 sscreen->b.get_vendor = si_get_vendor;
1032 sscreen->b.get_device_vendor = si_get_device_vendor;
1033 sscreen->b.get_param = si_get_param;
1034 sscreen->b.get_paramf = si_get_paramf;
1035 sscreen->b.get_compute_param = si_get_compute_param;
1036 sscreen->b.get_timestamp = si_get_timestamp;
1037 sscreen->b.get_shader_param = si_get_shader_param;
1038 sscreen->b.get_compiler_options = si_get_compiler_options;
1039 sscreen->b.get_device_uuid = si_get_device_uuid;
1040 sscreen->b.get_driver_uuid = si_get_driver_uuid;
1041 sscreen->b.query_memory_info = si_query_memory_info;
1042 sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
1044 if (sscreen->info.ip[AMD_IP_UVD].num_queues || sscreen->info.has_video_hw.vcn_decode ||
1045 sscreen->info.ip[AMD_IP_VCN_JPEG].num_queues || sscreen->info.ip[AMD_IP_VCE].num_queues ||
1046 sscreen->info.ip[AMD_IP_UVD_ENC].num_queues || sscreen->info.ip[AMD_IP_VCN_ENC].num_queues) {
1047 sscreen->b.get_video_param = si_get_video_param;
1048 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
1050 sscreen->b.get_video_param = si_get_video_param_no_video_hw;
1051 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
1054 si_init_renderer_string(sscreen);
1058 sscreen->info.gfx_level >= GFX9 && sscreen->options.force_use_fma32;
1088 .lower_ffma16 = sscreen->info.gfx_level < GFX9,
1089 .lower_ffma32 = sscreen->info.gfx_level < GFX10_3 && !force_fma32,
1091 .fuse_ffma16 = sscreen->info.gfx_level >= GFX9,
1092 .fuse_ffma32 = sscreen->info.gfx_level >= GFX10_3 || force_fma32,
1108 .has_sdot_4x8 = sscreen->info.has_accelerated_dot_product,
1109 .has_udot_4x8 = sscreen->info.has_accelerated_dot_product,
1110 .has_dot_2x16 = sscreen->info.has_accelerated_dot_product,
1116 .support_16bit_alu = sscreen->info.gfx_level >= GFX8,
1117 .vectorize_vec2_16bit = sscreen->info.has_packed_math_16bit,
1141 sscreen->nir_options = nir_options;