Lines Matching refs:sctx
38 static void si_dump_bo_list(struct si_context *sctx, const struct radeon_saved_cs *saved, FILE *f);
294 static void si_dump_mmapped_reg(struct si_context *sctx, FILE *f, unsigned offset)
296 struct radeon_winsys *ws = sctx->ws;
300 ac_dump_reg(f, sctx->gfx_level, offset, value, ~0);
303 static void si_dump_debug_registers(struct si_context *sctx, FILE *f)
306 si_dump_mmapped_reg(sctx, f, R_008010_GRBM_STATUS);
309 if (!sctx->screen->info.is_amdgpu) {
314 si_dump_mmapped_reg(sctx, f, R_008008_GRBM_STATUS2);
315 si_dump_mmapped_reg(sctx, f, R_008014_GRBM_STATUS_SE0);
316 si_dump_mmapped_reg(sctx, f, R_008018_GRBM_STATUS_SE1);
317 si_dump_mmapped_reg(sctx, f, R_008038_GRBM_STATUS_SE2);
318 si_dump_mmapped_reg(sctx, f, R_00803C_GRBM_STATUS_SE3);
319 si_dump_mmapped_reg(sctx, f, R_00D034_SDMA0_STATUS_REG);
320 si_dump_mmapped_reg(sctx, f, R_00D834_SDMA1_STATUS_REG);
321 if (sctx->gfx_level <= GFX8) {
322 si_dump_mmapped_reg(sctx, f, R_000E50_SRBM_STATUS);
323 si_dump_mmapped_reg(sctx, f, R_000E4C_SRBM_STATUS2);
324 si_dump_mmapped_reg(sctx, f, R_000E54_SRBM_STATUS3);
326 si_dump_mmapped_reg(sctx, f, R_008680_CP_STAT);
327 si_dump_mmapped_reg(sctx, f, R_008674_CP_STALLED_STAT1);
328 si_dump_mmapped_reg(sctx, f, R_008678_CP_STALLED_STAT2);
329 si_dump_mmapped_reg(sctx, f, R_008670_CP_STALLED_STAT3);
330 si_dump_mmapped_reg(sctx, f, R_008210_CP_CPC_STATUS);
331 si_dump_mmapped_reg(sctx, f, R_008214_CP_CPC_BUSY_STAT);
332 si_dump_mmapped_reg(sctx, f, R_008218_CP_CPC_STALLED_STAT1);
333 si_dump_mmapped_reg(sctx, f, R_00821C_CP_CPF_STATUS);
334 si_dump_mmapped_reg(sctx, f, R_008220_CP_CPF_BUSY_STAT);
335 si_dump_mmapped_reg(sctx, f, R_008224_CP_CPF_STALLED_STAT1);
389 void si_print_current_ib(struct si_context *sctx, FILE *f)
391 si_parse_current_ib(f, &sctx->gfx_cs, 0, sctx->gfx_cs.prev_dw + sctx->gfx_cs.current.cdw,
392 NULL, 0, "GFX", sctx->gfx_level);
469 void si_log_hw_flush(struct si_context *sctx)
471 if (!sctx->log)
474 si_log_cs(sctx, sctx->log, true);
476 if (&sctx->b == sctx->screen->aux_context) {
484 dd_write_header(f, &sctx->screen->b, 0);
487 u_log_new_page_print(sctx->log, f);
532 static void si_dump_bo_list(struct si_context *sctx, const struct radeon_saved_cs *saved, FILE *f)
548 const unsigned page_size = sctx->screen->info.gart_page_size;
581 static void si_dump_framebuffer(struct si_context *sctx, struct u_log_context *log)
583 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
593 si_print_texture_info(sctx->screen, tex, log);
600 si_print_texture_info(sctx->screen, tex, log);
746 static void si_dump_descriptors(struct si_context *sctx, gl_shader_stage stage,
751 &sctx->descriptors[SI_DESCS_FIRST_SHADER + processor * SI_NUM_SHADER_DESCS];
764 sctx->const_and_shader_buffers[processor].enabled_mask >> SI_NUM_SHADER_BUFFERS;
768 (sctx->const_and_shader_buffers[processor].enabled_mask &
771 enabled_samplers = sctx->samplers[processor].enabled_mask;
772 enabled_images = sctx->images[processor].enabled_mask;
775 if (stage == MESA_SHADER_VERTEX && sctx->vb_descriptors_buffer &&
776 sctx->vb_descriptors_gpu_list) {
780 desc.buffer = sctx->vb_descriptors_buffer;
781 desc.list = sctx->vb_descriptors_gpu_list;
782 desc.gpu_list = sctx->vb_descriptors_gpu_list;
784 desc.num_active_slots = sctx->vertex_elements->vb_desc_list_alloc_size / 16;
786 si_dump_descriptor_list(sctx->screen, &desc, name, " - Vertex buffer", 4, info->num_inputs,
790 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS], name,
793 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_CONST_AND_SHADER_BUFFERS], name,
796 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES], name,
799 si_dump_descriptor_list(sctx->screen, &descs[SI_SHADER_DESCS_SAMPLERS_AND_IMAGES], name,
803 static void si_dump_gfx_descriptors(struct si_context *sctx,
810 si_dump_descriptors(sctx, state->cso->stage, &state->cso->info, log);
813 static void si_dump_compute_descriptors(struct si_context *sctx, struct u_log_context *log)
815 if (!sctx->cs_shader_state.program)
818 si_dump_descriptors(sctx, MESA_SHADER_COMPUTE, NULL, log);
969 static void si_dump_annotated_shaders(struct si_context *sctx, FILE *f)
972 unsigned num_waves = ac_get_wave_info(sctx->gfx_level, waves);
976 si_print_annotated_shader(sctx->shader.vs.current, waves, num_waves, f);
977 si_print_annotated_shader(sctx->shader.tcs.current, waves, num_waves, f);
978 si_print_annotated_shader(sctx->shader.tes.current, waves, num_waves, f);
979 si_print_annotated_shader(sctx->shader.gs.current, waves, num_waves, f);
980 si_print_annotated_shader(sctx->shader.ps.current, waves, num_waves, f);
1020 struct si_context *sctx = (struct si_context *)ctx;
1022 if (sctx->log)
1023 u_log_flush(sctx->log);
1026 si_dump_debug_registers(sctx, f);
1028 si_dump_annotated_shaders(sctx, f);
1034 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log)
1039 si_dump_framebuffer(sctx, log);
1041 si_dump_gfx_shader(sctx, &sctx->shader.vs, log);
1042 si_dump_gfx_shader(sctx, &sctx->shader.tcs, log);
1043 si_dump_gfx_shader(sctx, &sctx->shader.tes, log);
1044 si_dump_gfx_shader(sctx, &sctx->shader.gs, log);
1045 si_dump_gfx_shader(sctx, &sctx->shader.ps, log);
1047 si_dump_descriptor_list(sctx->screen, &sctx->descriptors[SI_DESCS_INTERNAL], "", "RW buffers",
1048 4, sctx->descriptors[SI_DESCS_INTERNAL].num_active_slots, si_identity,
1050 si_dump_gfx_descriptors(sctx, &sctx->shader.vs, log);
1051 si_dump_gfx_descriptors(sctx, &sctx->shader.tcs, log);
1052 si_dump_gfx_descriptors(sctx, &sctx->shader.tes, log);
1053 si_dump_gfx_descriptors(sctx, &sctx->shader.gs, log);
1054 si_dump_gfx_descriptors(sctx, &sctx->shader.ps, log);
1057 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log)
1062 si_dump_compute_shader(sctx, log);
1063 si_dump_compute_descriptors(sctx, log);
1066 void si_check_vm_faults(struct si_context *sctx, struct radeon_saved_cs *saved, enum amd_ip_type ring)
1068 struct pipe_screen *screen = sctx->b.screen;
1073 if (!ac_vm_fault_occured(sctx->gfx_level, &sctx->dmesg_timestamp, &addr))
1088 if (sctx->apitrace_call_number)
1089 fprintf(f, "Last apitrace call: %u\n\n", sctx->apitrace_call_number);
1096 si_log_draw_state(sctx, &log);
1097 si_log_compute_state(sctx, &log);
1098 si_log_cs(sctx, &log, true);
1115 void si_init_debug_functions(struct si_context *sctx)
1117 sctx->b.dump_debug_state = si_dump_debug_state;
1122 if (sctx->screen->debug_flags & DBG(CHECK_VM))
1123 ac_vm_fault_occured(sctx->gfx_level, &sctx->dmesg_timestamp, NULL);