Lines Matching refs:sscreen
36 #define COMPUTE_DBG(sscreen, fmt, args...) \
38 if ((sscreen->debug_flags & DBG(COMPUTE))) \
117 struct si_screen *sscreen = sel->screen;
121 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
122 compiler = &sscreen->compiler[thread_index];
125 si_init_compiler(sscreen, compiler);
128 si_nir_scan_shader(sscreen, sel->nir, &sel->info);
130 si_get_active_slot_masks(sscreen, &sel->info, &sel->active_const_and_shader_buffers,
158 if (sscreen->info.gfx_level < GFX11)
180 simple_mtx_lock(&sscreen->shader_cache_mutex);
182 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
183 simple_mtx_unlock(&sscreen->shader_cache_mutex);
185 if (!si_shader_binary_upload(sscreen, shader, 0))
188 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
189 si_shader_dump(sscreen, shader, debug, stderr, true);
191 simple_mtx_unlock(&sscreen->shader_cache_mutex);
193 if (!si_create_shader_variant(sscreen, compiler, &program->shader, debug)) {
200 sscreen->info.wave64_vgpr_alloc_granularity == 8) ? 8 : 4)) |
203 S_00B848_WGP_MODE(sscreen->info.gfx_level >= GFX10) |
206 if (sscreen->info.gfx_level < GFX10) {
221 simple_mtx_lock(&sscreen->shader_cache_mutex);
222 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
223 simple_mtx_unlock(&sscreen->shader_cache_mutex);
233 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
239 sel->screen = sscreen;
246 program->shader.wave_size = si_determine_wave_size(sscreen, &program->shader);
262 p_atomic_inc(&sscreen->num_shaders_created);
802 struct si_screen *sscreen = sctx->screen;
822 ac_get_compute_resource_limits(&sscreen->info, waves_per_threadgroup,
933 struct si_screen *sscreen = sctx->screen;
937 bool cs_regalloc_hang = sscreen->info.has_cs_regalloc_hang_bug &&