Lines Matching defs:sel
62 const struct si_shader_selector *sel = &program->sel;
69 (struct ac_rtld_open_info){.info = &sel->screen->info,
113 struct si_shader_selector *sel = &program->sel;
116 struct util_debug_callback *debug = &sel->compiler_ctx_state.debug;
117 struct si_screen *sscreen = sel->screen;
128 si_nir_scan_shader(sscreen, sel->nir, &sel->info);
130 si_get_active_slot_masks(sscreen, &sel->info, &sel->active_const_and_shader_buffers,
131 &sel->active_samplers_and_images);
138 unsigned user_sgprs = SI_NUM_RESOURCE_SGPRS + (sel->info.uses_grid_size ? 3 : 0) +
139 (sel->info.uses_variable_block_size ? 1 : 0) +
140 sel->info.base.cs.user_data_components_amd;
144 for (unsigned i = 0; i < MIN2(3, sel->info.base.num_ssbos) && user_sgprs <= 12; i++) {
147 sel->cs_shaderbufs_sgpr_index = user_sgprs;
149 sel->cs_num_shaderbufs_in_user_sgprs++;
153 unsigned non_fmask_images = u_bit_consecutive(0, sel->info.base.num_images);
159 non_fmask_images &= ~sel->info.base.msaa_images[0];
162 unsigned num_sgprs = BITSET_TEST(sel->info.base.image_buffers, i) ? 4 : 8;
169 sel->cs_images_sgpr_index = user_sgprs;
171 sel->cs_num_images_in_user_sgprs++;
173 sel->cs_images_num_sgprs = user_sgprs - sel->cs_images_sgpr_index;
177 si_get_ir_cache_key(sel, false, false, shader->wave_size, ir_sha1_cache_key);
212 S_00B84C_TGID_X_EN(sel->info.uses_block_id[0]) |
213 S_00B84C_TGID_Y_EN(sel->info.uses_block_id[1]) |
214 S_00B84C_TGID_Z_EN(sel->info.uses_block_id[2]) |
215 S_00B84C_TG_SIZE_EN(sel->info.uses_subgroup_info) |
216 S_00B84C_TIDIG_COMP_CNT(sel->info.uses_thread_id[2]
218 : sel->info.uses_thread_id[1] ? 1 : 0) |
226 ralloc_free(sel->nir);
227 sel->nir = NULL;
235 struct si_shader_selector *sel = &program->sel;
237 pipe_reference_init(&sel->base.reference, 1);
238 sel->stage = MESA_SHADER_COMPUTE;
239 sel->screen = sscreen;
240 sel->const_and_shader_buf_descriptors_index =
242 sel->sampler_and_images_descriptors_index =
244 sel->info.base.shared_size = cso->req_local_mem;
245 program->shader.selector = &program->sel;
254 sel->nir = tgsi_to_nir(cso->prog, ctx->screen, true);
257 sel->nir = (struct nir_shader *)cso->prog;
260 sel->compiler_ctx_state.debug = sctx->debug;
261 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
264 si_schedule_initial_compile(sctx, MESA_SHADER_COMPUTE, &sel->ready, &sel->compiler_ctx_state,
299 struct si_shader_selector *sel = &program->sel;
307 util_queue_fence_wait(&sel->ready);
311 sel->active_const_and_shader_buffers);
313 sel->active_samplers_and_images);
530 lds_blocks += align(program->sel.info.base.shared_size, 256) >> 8;
532 lds_blocks += align(program->sel.info.base.shared_size, 512) >> 9;
681 dispatch.group_segment_size = util_cpu_to_le32(program->sel.info.base.shared_size);
760 struct si_shader_selector *sel = &program->sel;
765 12 * sel->info.uses_grid_size;
766 unsigned cs_user_data_reg = block_size_reg + 4 * program->sel.info.uses_variable_block_size;
770 if (sel->info.uses_grid_size) {
788 if (sel->info.uses_variable_block_size) {
793 if (sel->info.base.cs.user_data_components_amd) {
794 radeon_set_sh_reg_seq(cs_user_data_reg, sel->info.base.cs.user_data_components_amd);
795 radeon_emit_array(sctx->cs_user_data, sel->info.base.cs.user_data_components_amd);
901 struct si_shader_info *info = &sctx->cs_shader_state.program->sel.info;
1045 BITFIELD_MASK(program->sel.info.base.num_images);
1064 struct si_shader_selector *sel = &program->sel;
1067 util_queue_drop_job(&sel->screen->shader_compiler_queue, &sel->ready);
1068 util_queue_fence_destroy(&sel->ready);
1076 ralloc_free(program->sel.nir);