Lines Matching defs:tex
107 static bool si_alloc_separate_cmask(struct si_screen *sscreen, struct si_texture *tex)
114 if (tex->cmask_buffer)
117 if (!tex->surface.cmask_size)
120 tex->cmask_buffer =
122 tex->surface.cmask_size, 1 << tex->surface.cmask_alignment_log2);
123 if (tex->cmask_buffer == NULL)
126 tex->cmask_base_address_reg = tex->cmask_buffer->gpu_address >> 8;
127 tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
133 static bool si_set_clear_color(struct si_texture *tex, enum pipe_format surface_format,
140 if (tex->surface.bpe == 16) {
149 if (tex->swap_rgb_to_bgr)
155 if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
158 memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t));
420 bool vi_dcc_get_clear_info(struct si_context *sctx, struct si_texture *tex, unsigned level,
423 struct pipe_resource *dcc_buffer = &tex->buffer.b.b;
424 uint64_t dcc_offset = tex->surface.meta_offset;
427 assert(vi_dcc_enabled(tex, level));
433 if (sctx->gfx_level < GFX11 && tex->buffer.b.b.nr_storage_samples >= 4)
436 unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
440 dcc_offset += tex->surface.u.gfx9.meta_levels[level].offset;
441 clear_size = tex->surface.u.gfx9.meta_levels[level].size;
442 } else if (tex->buffer.b.b.last_level == 0) {
444 clear_size = tex->surface.meta_size;
456 if (tex->buffer.b.b.last_level > 0)
461 if (tex->buffer.b.b.nr_storage_samples >= 4) {
467 clear_size = tex->surface.meta_size;
469 unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
472 if (!tex->surface.u.legacy.color.dcc_level[level].dcc_fast_clear_size)
479 if (tex->buffer.b.b.nr_storage_samples >= 4 && num_layers > 1)
482 dcc_offset += tex->surface.u.legacy.color.dcc_level[level].dcc_offset;
483 clear_size = tex->surface.u.legacy.color.dcc_level[level].dcc_fast_clear_size;
494 static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen, struct si_texture *tex)
496 if (sscreen->info.gfx_level >= GFX10 || tex->buffer.b.is_shared ||
497 tex->buffer.b.b.nr_samples <= 1 ||
498 tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
502 tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
503 assert(tex->buffer.b.b.last_level == 0);
507 assert(tex->surface.u.gfx9.swizzle_mode >= 4);
517 assert(tex->surface.u.gfx9.swizzle_mode % 4 != 0);
519 switch (tex->last_msaa_resolve_target_micro_mode) {
521 tex->surface.u.gfx9.swizzle_mode &= ~0x3;
522 tex->surface.u.gfx9.swizzle_mode += 2; /* D */
525 tex->surface.u.gfx9.swizzle_mode &= ~0x3;
526 tex->surface.u.gfx9.swizzle_mode += 1; /* S */
529 tex->surface.u.gfx9.swizzle_mode &= ~0x3;
530 tex->surface.u.gfx9.swizzle_mode += 3; /* R */
541 switch (tex->last_msaa_resolve_target_micro_mode) {
543 tex->surface.u.legacy.tiling_index[0] = 10;
546 tex->surface.u.legacy.tiling_index[0] = 14;
549 tex->surface.u.legacy.tiling_index[0] = 28;
556 switch (tex->last_msaa_resolve_target_micro_mode) {
558 switch (tex->surface.bpe) {
560 tex->surface.u.legacy.tiling_index[0] = 10;
563 tex->surface.u.legacy.tiling_index[0] = 11;
566 tex->surface.u.legacy.tiling_index[0] = 12;
571 switch (tex->surface.bpe) {
573 tex->surface.u.legacy.tiling_index[0] = 14;
576 tex->surface.u.legacy.tiling_index[0] = 15;
579 tex->surface.u.legacy.tiling_index[0] = 16;
582 tex->surface.u.legacy.tiling_index[0] = 17;
592 tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode;
597 static uint32_t si_get_htile_clear_value(struct si_texture *tex, float depth)
610 if (tex->htile_stencil_disabled) {
687 struct si_texture *tex = (struct si_texture *)fb->cbufs[i]->texture;
688 unsigned level = fb->cbufs[i]->u.tex.level;
689 unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
692 if (fb->cbufs[i]->u.tex.first_layer != 0 ||
693 fb->cbufs[i]->u.tex.last_layer != num_layers - 1) {
699 si_set_optimal_micro_tile_mode(sctx->screen, tex);
701 if (tex->swap_rgb_to_bgr_on_next_clear) {
702 assert(!tex->swap_rgb_to_bgr);
703 assert(tex->buffer.b.b.nr_samples >= 2);
704 tex->swap_rgb_to_bgr = true;
705 tex->swap_rgb_to_bgr_on_next_clear = false;
712 if (tex->surface.is_linear) {
723 bool too_small = tex->buffer.b.b.nr_samples <= 1 && fb_too_small;
728 if (vi_dcc_enabled(tex, level)) {
739 if (!gfx8_get_dcc_clear_parameters(sctx->screen, tex->buffer.b.b.format,
752 tex->buffer.b.is_shared &&
753 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
766 if (tex->buffer.b.b.nr_samples >= 2 && eliminate_needed &&
767 !sctx->screen->allow_dcc_msaa_clear_to_reg_for_bpp[util_logbase2(tex->surface.bpe)])
772 if (!vi_dcc_get_clear_info(sctx, tex, level, reset_value, &info[num_clears]))
778 si_mark_display_dcc_dirty(sctx, tex);
781 if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
784 si_init_buffer_clear(&info[num_clears++], &tex->cmask_buffer->b.b,
785 tex->surface.cmask_offset, tex->surface.cmask_size, 0xCCCCCCCC);
800 if (tex->buffer.b.is_shared &&
801 !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
808 if (tex->surface.bpe > 8) {
816 /* Disable fast clear if tex is encrypted */
817 if (tex->buffer.flags & RADEON_FLAG_ENCRYPTED)
829 if (num_layers > 1 && tex->buffer.b.b.last_level > 0)
832 if (!si_alloc_separate_cmask(sctx->screen, tex))
837 cmask_offset = tex->surface.cmask_offset + tex->surface.u.gfx9.color.cmask_level0.offset;
838 clear_size = tex->surface.u.gfx9.color.cmask_level0.size;
839 } else if (tex->buffer.b.b.last_level == 0) {
841 cmask_offset = tex->surface.cmask_offset;
842 clear_size = tex->surface.cmask_size;
851 if (tex->buffer.b.b.last_level > 0)
854 if (!si_alloc_separate_cmask(sctx->screen, tex))
857 cmask_offset = tex->surface.cmask_offset;
858 clear_size = tex->surface.cmask_size;
860 if (!si_alloc_separate_cmask(sctx->screen, tex))
864 cmask_offset = tex->surface.cmask_offset;
865 clear_size = tex->surface.cmask_size;
870 si_init_buffer_clear(&info[num_clears++], &tex->cmask_buffer->b.b,
877 !(tex->dirty_level_mask & (1 << level))) {
879 tex->dirty_level_mask |= 1 << level;
880 si_set_sampler_depth_decompress_mask(sctx, tex);
895 if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {
904 unsigned zs_num_layers = zstex ? util_num_layers(&zstex->buffer.b.b, zsbuf->u.tex.level) : 0;
906 if (zstex && zsbuf->u.tex.first_layer == 0 &&
907 zsbuf->u.tex.last_layer == zs_num_layers - 1 &&
908 si_htile_enabled(zstex, zsbuf->u.tex.level, PIPE_MASK_ZS)) {
909 unsigned level = zsbuf->u.tex.level;
1131 struct si_texture *tex = (struct si_texture *)fb->cbufs[i]->texture;
1132 if (tex->surface.fmask_size == 0)
1133 tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
1137 if (zstex && zsbuf->u.tex.first_layer == 0 &&
1138 zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
1139 unsigned level = zsbuf->u.tex.level;
1203 zstex->depth_cleared_level_mask_once |= BITFIELD_BIT(zsbuf->u.tex.level);
1204 zstex->depth_cleared_level_mask |= BITFIELD_BIT(zsbuf->u.tex.level);
1211 zstex->stencil_cleared_level_mask_once |= BITFIELD_BIT(zsbuf->u.tex.level);
1226 dst->u.tex.first_layer == 0 &&
1227 dst->u.tex.last_layer == util_max_layer(dst->texture, dst->u.tex.level) &&
1272 (sctx->gfx_level >= GFX10 || !vi_dcc_enabled(sdst, dst->u.tex.level))) {
1304 static void si_clear_texture(struct pipe_context *pipe, struct pipe_resource *tex, unsigned level,
1308 struct si_texture *stex = (struct si_texture *)tex;
1312 tmpl.format = tex->format;
1313 tmpl.u.tex.first_layer = box->z;
1314 tmpl.u.tex.last_layer = box->z + box->depth - 1;
1315 tmpl.u.tex.level = level;
1316 sf = pipe->create_surface(pipe, tex, &tmpl);
1327 util_format_unpack_z_float(tex->format, &depth, data, 1);
1331 util_format_unpack_s_8uint(tex->format, &stencil, data, 1);
1339 util_format_unpack_rgba(tex->format, color.ui, data, 1);
1341 if (screen->is_format_supported(screen, tex->format, tex->target, 0, 0,