Lines Matching refs:usage
34 unsigned usage)
36 return sctx->ws->cs_is_buffer_referenced(&sctx->gfx_cs, buf, usage);
40 unsigned usage)
42 return sctx->ws->buffer_map(sctx->ws, resource->buf, &sctx->gfx_cs, usage);
56 switch (res->b.b.usage) {
152 /* Set expected VRAM and GART usage for the buffer. */
314 unsigned usage, const struct pipe_box *box,
321 if (usage & PIPE_MAP_THREAD_SAFE)
323 else if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
329 transfer->b.b.usage = usage;
338 unsigned level, unsigned usage, const struct pipe_box *box,
360 usage |= PIPE_MAP_PERSISTENT;
361 if (usage & PIPE_MAP_ONCE)
362 usage |= RADEON_MAP_TEMPORARY;
366 if (!(usage & (PIPE_MAP_UNSYNCHRONIZED | TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED)) &&
367 usage & PIPE_MAP_WRITE && !buf->b.is_shared &&
369 usage |= PIPE_MAP_UNSYNCHRONIZED;
373 if (usage & PIPE_MAP_DISCARD_RANGE && box->x == 0 && box->width == resource->width0) {
374 usage |= PIPE_MAP_DISCARD_WHOLE_RESOURCE;
381 if (usage & (PIPE_MAP_DISCARD_WHOLE_RESOURCE | PIPE_MAP_DISCARD_RANGE) &&
382 !(usage & PIPE_MAP_PERSISTENT) &&
384 usage &= ~(PIPE_MAP_DISCARD_WHOLE_RESOURCE | PIPE_MAP_UNSYNCHRONIZED);
385 usage |= PIPE_MAP_DISCARD_RANGE;
389 if (usage & PIPE_MAP_DISCARD_WHOLE_RESOURCE &&
390 !(usage & (PIPE_MAP_UNSYNCHRONIZED | TC_TRANSFER_MAP_NO_INVALIDATE))) {
391 assert(usage & PIPE_MAP_WRITE);
395 usage |= PIPE_MAP_UNSYNCHRONIZED;
398 usage |= PIPE_MAP_DISCARD_RANGE;
402 if (usage & PIPE_MAP_DISCARD_RANGE &&
403 ((!(usage & (PIPE_MAP_UNSYNCHRONIZED | PIPE_MAP_PERSISTENT))) ||
405 assert(usage & PIPE_MAP_WRITE);
422 if (usage & TC_TRANSFER_MAP_THREADED_UNSYNC)
433 return si_buffer_get_transfer(ctx, resource, usage, box, ptransfer, data, staging,
440 usage |= PIPE_MAP_UNSYNCHRONIZED;
444 else if (((usage & PIPE_MAP_READ) && !(usage & PIPE_MAP_PERSISTENT) &&
449 assert(!(usage & (TC_TRANSFER_MAP_THREADED_UNSYNC | PIPE_MAP_THREAD_SAFE)));
459 data = si_buffer_map(sctx, staging, usage & ~PIPE_MAP_UNSYNCHRONIZED);
466 return si_buffer_get_transfer(ctx, resource, usage, box, ptransfer, data, staging, 0);
472 data = si_buffer_map(sctx, buf, usage);
478 return si_buffer_get_transfer(ctx, resource, usage, box, ptransfer, data, NULL, 0);
505 if ((transfer->usage & required_usage) == required_usage) {
518 if (transfer->usage & PIPE_MAP_WRITE && !(transfer->usage & PIPE_MAP_FLUSH_EXPLICIT))
521 if (transfer->usage & (PIPE_MAP_ONCE | RADEON_MAP_TEMPORARY) &&
529 if (transfer->usage & PIPE_MAP_THREAD_SAFE) {
540 unsigned usage, unsigned offset, unsigned size, const void *data)
546 usage |= PIPE_MAP_WRITE;
548 if (!(usage & PIPE_MAP_DIRECTLY))
549 usage |= PIPE_MAP_DISCARD_RANGE;
552 map = si_buffer_transfer_map(ctx, buffer, 0, usage, &box, &transfer);
604 unsigned usage, unsigned size, unsigned alignment)
612 buffer.usage = usage;
622 unsigned usage, unsigned size, unsigned alignment)
624 return si_resource(pipe_aligned_buffer_create(screen, flags, usage, size, alignment));
679 /* Deduce the usage. */
683 res->b.b.usage = PIPE_USAGE_DEFAULT;
691 res->b.b.usage = PIPE_USAGE_STREAM;
693 res->b.b.usage = PIPE_USAGE_STAGING;