Lines Matching defs:res
45 void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res, uint64_t size,
48 struct si_texture *tex = (struct si_texture *)res;
50 res->bo_size = size;
51 res->bo_alignment_log2 = util_logbase2(alignment);
52 res->flags = 0;
53 res->texture_handle_allocated = false;
54 res->image_handle_allocated = false;
56 switch (res->b.b.usage) {
58 res->flags |= RADEON_FLAG_GTT_WC;
60 res->domains = RADEON_DOMAIN_VRAM;
62 res->domains = RADEON_DOMAIN_GTT;
67 res->domains = RADEON_DOMAIN_GTT;
75 res->domains = RADEON_DOMAIN_VRAM;
76 res->flags |= RADEON_FLAG_GTT_WC;
80 if (res->b.b.target == PIPE_BUFFER && res->b.b.flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
93 res->domains = RADEON_DOMAIN_GTT;
97 if ((res->b.b.target != PIPE_BUFFER && !tex->surface.is_linear) ||
98 res->b.b.flags & PIPE_RESOURCE_FLAG_UNMAPPABLE) {
99 res->domains = RADEON_DOMAIN_VRAM;
100 res->flags |= RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC;
104 if (res->b.b.bind & (PIPE_BIND_SHARED | PIPE_BIND_SCANOUT))
105 res->flags |= RADEON_FLAG_NO_SUBALLOC; /* shareable */
107 res->flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
109 if (res->b.b.bind & PIPE_BIND_PROTECTED ||
112 res->b.b.bind & (PIPE_BIND_SCANOUT | PIPE_BIND_DEPTH_STENCIL)))
113 res->flags |= RADEON_FLAG_ENCRYPTED;
115 if (res->b.b.flags & PIPE_RESOURCE_FLAG_ENCRYPTED)
116 res->flags |= RADEON_FLAG_ENCRYPTED;
119 res->flags &= ~RADEON_FLAG_GTT_WC;
121 if (res->b.b.flags & SI_RESOURCE_FLAG_READ_ONLY)
122 res->flags |= RADEON_FLAG_READ_ONLY;
124 if (res->b.b.flags & SI_RESOURCE_FLAG_32BIT)
125 res->flags |= RADEON_FLAG_32BIT;
127 if (res->b.b.flags & SI_RESOURCE_FLAG_DRIVER_INTERNAL)
128 res->flags |= RADEON_FLAG_DRIVER_INTERNAL;
130 if (res->b.b.flags & PIPE_RESOURCE_FLAG_SPARSE)
131 res->flags |= RADEON_FLAG_SPARSE;
138 res->b.b.flags & SI_RESOURCE_FLAG_GL2_BYPASS)
139 res->flags |= RADEON_FLAG_GL2_BYPASS;
141 if (res->b.b.flags & SI_RESOURCE_FLAG_DISCARDABLE &&
144 assert(res->domains == RADEON_DOMAIN_VRAM);
145 res->flags |= RADEON_FLAG_DISCARDABLE;
148 if (res->domains == RADEON_DOMAIN_VRAM &&
150 res->flags |= RADEON_FLAG_MALL_NOALLOC;
153 res->memory_usage_kb = MAX2(1, size / 1024);
155 if (res->domains & RADEON_DOMAIN_VRAM) {
162 !res->b.cpu_storage && /* TODO: The CPU storage breaks this. */
164 res->b.b.flags |= PIPE_RESOURCE_FLAG_DONT_MAP_DIRECTLY;
168 bool si_alloc_resource(struct si_screen *sscreen, struct si_resource *res)
173 new_buf = sscreen->ws->buffer_create(sscreen->ws, res->bo_size, 1 << res->bo_alignment_log2,
174 res->domains, res->flags);
179 /* Replace the pointer such that if res->buf wasn't NULL, it won't be
183 old_buf = res->buf;
184 res->buf = new_buf; /* should be atomic */
185 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf);
187 if (res->flags & RADEON_FLAG_32BIT) {
188 uint64_t start = res->gpu_address;
189 uint64_t last = start + res->bo_size - 1;
199 util_range_set_empty(&res->valid_buffer_range);
200 res->TC_L2_dirty = false;
203 if (sscreen->debug_flags & DBG(VM) && res->b.b.target == PIPE_BUFFER) {
205 res->gpu_address, res->gpu_address + res->buf->size, res->buf->size);
208 if (res->b.b.flags & SI_RESOURCE_FLAG_CLEAR)
209 si_screen_clear_buffer(sscreen, &res->b.b, 0, res->bo_size, 0, SI_OP_SYNC_AFTER);
664 struct si_resource *res = si_alloc_buffer_struct(screen, templ, false);
666 if (!res)
675 res->flags |= sscreen->ws->buffer_get_flags(imported_buf);
683 res->b.b.usage = PIPE_USAGE_DEFAULT;
691 res->b.b.usage = PIPE_USAGE_STREAM;
693 res->b.b.usage = PIPE_USAGE_STAGING;
696 si_init_resource_fields(sscreen, res, imported_buf->size,
699 res->b.is_shared = true;
700 res->b.buffer_id_unique = util_idalloc_mt_alloc(&sscreen->buffer_ids);
701 res->buf = imported_buf;
702 res->gpu_address = sscreen->ws->buffer_get_virtual_address(res->buf) + offset;
703 res->domains = domains;
704 res->flags = flags;
706 if (res->flags & RADEON_FLAG_NO_CPU_ACCESS)
707 res->b.b.flags |= PIPE_RESOURCE_FLAG_UNMAPPABLE;
709 util_range_add(&res->b.b, &res->valid_buffer_range, 0, templ->width0);
710 util_range_add(&res->b.b, &res->b.valid_buffer_range, 0, templ->width0);
712 return &res->b.b;
725 static bool si_buffer_commit(struct si_context *ctx, struct si_resource *res,
728 return ctx->ws->buffer_commit(ctx->ws, res->buf, box->x, box->width, commit);
735 struct si_resource *res = si_resource(resource);
745 ctx->ws->cs_is_buffer_referenced(&ctx->gfx_cs, res->buf, RADEON_USAGE_READWRITE)) {
751 return si_buffer_commit(ctx, res, box, commit);
753 return si_texture_commit(ctx, res, level, box, commit);