Lines Matching defs:rtex
41 struct r600_texture *rtex);
175 struct r600_texture *rtex, unsigned level,
180 *stride = rtex->surface.u.legacy.level[level].nblk_x *
181 rtex->surface.bpe;
182 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
183 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
186 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
190 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256 +
191 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
192 (box->y / rtex->surface.blk_h *
193 rtex->surface.u.legacy.level[level].nblk_x +
194 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
272 struct r600_texture *rtex,
275 struct radeon_surf *surface = &rtex->surface;
317 struct r600_texture *rtex)
325 ctx->flush_resource(ctx, &rtex->resource.b.b);
333 struct r600_texture *rtex)
335 if (!rtex->cmask.size)
338 assert(rtex->resource.b.b.nr_samples <= 1);
341 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
342 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
343 rtex->dirty_level_mask = 0;
345 rtex->cb_color_info &= ~EG_S_028C70_FAST_CLEAR(1);
347 if (rtex->cmask_buffer != &rtex->resource)
348 r600_resource_reference(&rtex->cmask_buffer, NULL);
356 struct r600_texture *rtex,
362 struct pipe_resource templ = rtex->resource.b.b;
371 if (rtex->resource.b.is_shared)
375 if (rtex->surface.is_linear)
398 &rtex->resource.b.b, i, &box);
403 r600_texture_discard_cmask(rctx->screen, rtex);
406 /* Replace the structure fields of rtex. */
407 rtex->resource.b.b.bind = templ.bind;
408 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
409 rtex->resource.gpu_address = new_tex->resource.gpu_address;
410 rtex->resource.vram_usage = new_tex->resource.vram_usage;
411 rtex->resource.gart_usage = new_tex->resource.gart_usage;
412 rtex->resource.bo_size = new_tex->resource.bo_size;
413 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
414 rtex->resource.domains = new_tex->resource.domains;
415 rtex->resource.flags = new_tex->resource.flags;
416 rtex->size = new_tex->size;
417 rtex->db_render_format = new_tex->db_render_format;
418 rtex->db_compatible = new_tex->db_compatible;
419 rtex->can_sample_z = new_tex->can_sample_z;
420 rtex->can_sample_s = new_tex->can_sample_s;
421 rtex->surface = new_tex->surface;
422 rtex->fmask = new_tex->fmask;
423 rtex->cmask = new_tex->cmask;
424 rtex->cb_color_info = new_tex->cb_color_info;
425 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
426 rtex->htile_offset = new_tex->htile_offset;
427 rtex->depth_cleared = new_tex->depth_cleared;
428 rtex->stencil_cleared = new_tex->stencil_cleared;
429 rtex->non_disp_tiling = new_tex->non_disp_tiling;
430 rtex->framebuffers_bound = new_tex->framebuffers_bound;
433 assert(!rtex->htile_offset);
434 assert(!rtex->cmask.size);
435 assert(!rtex->fmask.size);
436 assert(!rtex->is_depth);
450 struct r600_texture *rtex = (struct r600_texture*)resource;
454 if (!rscreen || !rtex)
458 offset = (uint64_t)rtex->surface.u.legacy.level[0].offset_256B * 256;
459 stride = rtex->surface.u.legacy.level[0].nblk_x *
460 rtex->surface.bpe;
479 struct r600_texture *rtex = (struct r600_texture*)resource;
491 if (resource->nr_samples > 1 || rtex->is_depth)
496 rtex->surface.tile_swizzle) {
498 r600_reallocate_texture_inplace(rctx, rtex,
503 assert(rtex->surface.tile_swizzle == 0);
507 rtex->cmask.size) {
509 r600_eliminate_fast_color_clear(rctx, rtex);
514 if (rtex->cmask.size)
515 r600_texture_discard_cmask(rscreen, rtex);
520 r600_texture_init_metadata(rscreen, rtex, &metadata);
525 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
579 struct r600_texture *rtex = (struct r600_texture*)ptex;
580 struct r600_resource *resource = &rtex->resource;
582 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
585 if (rtex->cmask_buffer != &rtex->resource) {
586 r600_resource_reference(&rtex->cmask_buffer, NULL);
589 FREE(rtex);
594 struct r600_texture *rtex,
599 struct pipe_resource templ = rtex->resource.b.b;
606 flags = rtex->surface.flags | RADEON_SURF_FMASK;
609 fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
610 fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
611 fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
612 fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
658 struct r600_texture *rtex)
660 r600_texture_get_fmask_info(rscreen, rtex,
661 rtex->resource.b.b.nr_samples, &rtex->fmask);
663 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
664 rtex->size = rtex->fmask.offset + rtex->fmask.size;
668 struct r600_texture *rtex,
685 unsigned pitch_elements = align(rtex->resource.b.b.width0, macro_tile_width);
686 unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
697 out->size = util_num_layers(&rtex->resource.b.b, 0) *
702 struct r600_texture *rtex)
704 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
706 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
707 rtex->size = rtex->cmask.offset + rtex->cmask.size;
709 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
713 struct r600_texture *rtex)
715 if (rtex->cmask_buffer)
718 assert(rtex->cmask.size == 0);
720 r600_texture_get_cmask_info(rscreen, rtex, &rtex->cmask);
722 rtex->cmask_buffer = (struct r600_resource *)
726 rtex->cmask.size,
727 rtex->cmask.alignment);
728 if (rtex->cmask_buffer == NULL) {
729 rtex->cmask.size = 0;
734 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
736 rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
751 struct r600_texture *rtex)
757 rtex->surface.meta_size = 0;
761 (rtex->resource.b.b.width0 > 7680 ||
762 rtex->resource.b.b.height0 > 7680))
791 width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
792 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
800 rtex->surface.meta_alignment_log2 = util_logbase2(base_align);
801 rtex->surface.meta_size =
802 util_num_layers(&rtex->resource.b.b, 0) *
807 struct r600_texture *rtex)
809 r600_texture_get_htile_size(rscreen, rtex);
811 if (!rtex->surface.meta_size)
814 rtex->htile_offset = align(rtex->size, 1 << rtex->surface.meta_alignment_log2);
815 rtex->size = rtex->htile_offset + rtex->surface.meta_size;
819 struct r600_texture *rtex, struct u_log_context *log)
827 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
828 rtex->resource.b.b.depth0, rtex->surface.blk_w,
829 rtex->surface.blk_h,
830 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
831 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
832 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
836 rtex->surface.surf_size, 1 << rtex->surface.surf_alignment_log2, rtex->surface.u.legacy.bankw,
837 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
838 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
839 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
841 if (rtex->fmask.size)
844 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
845 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
846 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
848 if (rtex->cmask.size)
851 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
852 rtex->cmask.slice_tile_max);
854 if (rtex->htile_offset)
857 rtex->htile_offset, rtex->surface.meta_size,
858 1 << rtex->surface.meta_alignment_log2);
860 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
864 i, (uint64_t)rtex->surface.u.legacy.level[i].offset_256B * 256,
865 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
866 u_minify(rtex->resource.b.b.width0, i),
867 u_minify(rtex->resource.b.b.height0, i),
868 u_minify(rtex->resource.b.b.depth0, i),
869 rtex->surface.u.legacy.level[i].nblk_x,
870 rtex->surface.u.legacy.level[i].nblk_y,
871 rtex->surface.u.legacy.level[i].mode,
872 rtex->surface.u.legacy.tiling_index[i]);
874 if (rtex->surface.has_stencil) {
876 rtex->surface.u.legacy.stencil_tile_split);
877 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
882 i, (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].offset_256B * 256,
883 (uint64_t)rtex->surface.u.legacy.zs.stencil_level[i].slice_size_dw * 4,
884 u_minify(rtex->resource.b.b.width0, i),
885 u_minify(rtex->resource.b.b.height0, i),
886 u_minify(rtex->resource.b.b.depth0, i),
887 rtex->surface.u.legacy.zs.stencil_level[i].nblk_x,
888 rtex->surface.u.legacy.zs.stencil_level[i].nblk_y,
889 rtex->surface.u.legacy.zs.stencil_level[i].mode,
890 rtex->surface.u.legacy.zs.stencil_tiling_index[i]);
902 struct r600_texture *rtex;
906 rtex = CALLOC_STRUCT(r600_texture);
907 if (!rtex)
910 resource = &rtex->resource;
916 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
918 rtex->surface = *surface;
919 rtex->size = rtex->surface.surf_size;
920 rtex->db_render_format = base->format;
925 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
927 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
929 if (rtex->is_depth) {
933 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
934 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
936 if (rtex->resource.b.b.nr_samples <= 1 &&
937 (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
938 rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT))
939 rtex->can_sample_z = true;
944 rtex->db_compatible = true;
947 r600_texture_allocate_htile(rscreen, rtex);
952 r600_texture_allocate_fmask(rscreen, rtex);
953 r600_texture_allocate_cmask(rscreen, rtex);
954 rtex->cmask_buffer = &rtex->resource;
956 if (!rtex->fmask.size || !rtex->cmask.size) {
957 FREE(rtex);
965 r600_init_resource_fields(rscreen, resource, rtex->size,
966 1 << rtex->surface.surf_alignment_log2);
969 FREE(rtex);
984 if (rtex->cmask.size) {
986 r600_screen_clear_buffer(rscreen, &rtex->cmask_buffer->b.b,
987 rtex->cmask.offset, rtex->cmask.size,
990 if (rtex->htile_offset) {
993 r600_screen_clear_buffer(rscreen, &rtex->resource.b.b,
994 rtex->htile_offset,
995 rtex->surface.meta_size,
1000 rtex->cmask.base_address_reg =
1001 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1005 rtex->resource.gpu_address,
1006 rtex->resource.gpu_address + rtex->resource.buf->size,
1015 r600_print_texture_info(rscreen, rtex, &log);
1021 return rtex;
1114 struct r600_texture *rtex;
1138 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1139 if (!rtex)
1142 rtex->resource.b.is_shared = true;
1143 rtex->resource.external_usage = usage;
1145 assert(rtex->surface.tile_swizzle == 0);
1146 return &rtex->resource.b.b;
1153 struct r600_texture *rtex = (struct r600_texture*)texture;
1156 staging : &rtex->flushed_depth_texture;
1160 if (rtex->flushed_depth_texture)
1163 if (!rtex->can_sample_z && rtex->can_sample_s) {
1184 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1247 struct r600_texture *rtex,
1253 !rtex->resource.b.is_shared &&
1255 rtex->resource.b.b.last_level == 0 &&
1256 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1263 struct r600_texture *rtex)
1268 assert(!rtex->is_depth);
1269 assert(rtex->surface.is_linear);
1272 r600_alloc_resource(rscreen, &rtex->resource);
1275 rtex->cmask.base_address_reg =
1276 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1280 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1291 struct r600_texture *rtex = (struct r600_texture*)texture;
1302 if (!rtex->is_depth) {
1310 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1312 r600_can_invalidate_texture(rctx->screen, rtex,
1315 r600_reallocate_texture_inplace(rctx, rtex,
1329 if (!rtex->surface.is_linear)
1333 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1334 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1336 else if (r600_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1338 !rctx->ws->buffer_wait(rctx->ws, rtex->resource.buf, 0,
1341 if (r600_can_invalidate_texture(rctx->screen, rtex,
1343 r600_texture_invalidate_storage(rctx, rtex);
1357 if (rtex->is_depth) {
1360 if (rtex->resource.b.b.nr_samples > 1) {
1408 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1452 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1455 buf = &rtex->resource;
1474 struct r600_texture *rtex = (struct r600_texture*)texture;
1477 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1597 struct r600_texture *rtex = (struct r600_texture*)tex;
1609 if (rtex->is_depth) {
1618 if (rtex->surface.has_stencil) {
1709 static void evergreen_set_clear_color(struct r600_texture *rtex,
1717 if (rtex->surface.bpe == 16) {
1730 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
1877 struct r600_texture *rtex;
1923 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
1924 if (!rtex)
1932 rtex->resource.b.is_shared = true;
1933 rtex->resource.external_usage = PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE;
1935 return &rtex->resource.b.b;