Lines Matching defs:level
79 /* The CMASK clear is only enabled for the first level. */
113 blit.src.level = src_level;
117 blit.dst.level = dst_level;
143 src, transfer->level, &transfer->box);
147 rctx->dma_copy(ctx, dst, 0, 0, 0, 0, src, transfer->level,
163 r600_copy_region_with_blit(ctx, dst, transfer->level,
169 rctx->dma_copy(ctx, dst, transfer->level,
175 struct r600_texture *rtex, unsigned level,
180 *stride = rtex->surface.u.legacy.level[level].nblk_x *
182 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
183 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
186 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
188 /* Each texture is an array of mipmap levels. Each level is
190 return (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256 +
191 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
193 rtex->surface.u.legacy.level[level].nblk_x +
254 pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
255 /* old ddx on evergreen over estimate alignment for 1d, only 1 level
258 surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
259 surface->u.legacy.level[0].slice_size_dw =
260 ((uint64_t)pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y) / 4;
264 for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
265 surface->u.legacy.level[i].offset_256B += offset / 256;
279 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
281 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
289 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
458 offset = (uint64_t)rtex->surface.u.legacy.level[0].offset_256B * 256;
459 stride = rtex->surface.u.legacy.level[0].nblk_x *
525 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
643 assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
645 out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
650 out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
791 width = align(rtex->surface.u.legacy.level[0].nblk_x, cl_width * 8);
792 height = align(rtex->surface.u.legacy.level[0].nblk_y, cl_height * 8);
864 i, (uint64_t)rtex->surface.u.legacy.level[i].offset_256B * 256,
865 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
869 rtex->surface.u.legacy.level[i].nblk_x,
870 rtex->surface.u.legacy.level[i].nblk_y,
871 rtex->surface.u.legacy.level[i].mode,
925 rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
1221 * mipmap level.
1226 unsigned level, unsigned flags)
1238 if (box->depth > 1 && util_max_layer(orig, level) > 0) {
1285 unsigned level,
1308 level == 0 &&
1353 trans->b.b.level = level;
1373 r600_init_temp_resource_from_box(&resource, texture, box, level, 0);
1389 r600_copy_region_with_blit(ctx, temp, 0, 0, 0, 0, texture, level, box);
1396 r600_texture_get_offset(rctx->screen, staging_depth, level, NULL,
1409 level, level,
1414 level, box,
1425 r600_init_temp_resource_from_box(&resource, texture, box, level,
1452 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1478 ctx->resource_copy_region(ctx, texture, transfer->level,
1480 &rtransfer->staging->b.b, transfer->level,
1525 assert(templ->u.tex.first_layer <= util_max_layer(texture, templ->u.tex.level));
1526 assert(templ->u.tex.last_layer <= util_max_layer(texture, templ->u.tex.level));
1546 unsigned level = templ->u.tex.level;
1547 unsigned width = u_minify(tex->width0, level);
1548 unsigned height = u_minify(tex->height0, level);
1592 unsigned level,
1604 tmpl.u.tex.level = level;
1815 tex->dirty_level_mask |= 1 << fb->cbufs[i]->u.tex.level;