Lines Matching refs:rctx
37 static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable);
45 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
54 u_suballocator_alloc(&rctx->allocator_zeroed_memory, 4, 4,
82 void r600_streamout_buffers_dirty(struct r600_common_context *rctx)
84 struct r600_atom *begin = &rctx->streamout.begin_atom;
85 unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask);
86 unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask &
87 rctx->streamout.append_bitmask);
92 rctx->streamout.num_dw_for_end =
100 if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740)
106 (rctx->family > CHIP_R600 && rctx->family < CHIP_RS780 ? 2 : 0); /* SURFACE_BASE_UPDATE */
108 rctx->set_atom_dirty(rctx, begin, true);
110 r600_set_streamout_enable(rctx, true);
118 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
123 if (rctx->streamout.num_targets && rctx->streamout.begin_emitted) {
124 r600_emit_streamout_end(rctx);
129 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], targets[i]);
138 for (; i < rctx->streamout.num_targets; i++) {
139 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->streamout.targets[i], NULL);
142 rctx->streamout.enabled_mask = enabled_mask;
144 rctx->streamout.num_targets = num_targets;
145 rctx->streamout.append_bitmask = append_bitmask;
148 r600_streamout_buffers_dirty(rctx);
150 rctx->set_atom_dirty(rctx, &rctx->streamout.begin_atom, false);
151 r600_set_streamout_enable(rctx, false);
155 static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
157 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
161 if (rctx->gfx_level >= EVERGREEN) {
181 static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r600_atom *atom)
183 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
184 struct r600_so_target **t = rctx->streamout.targets;
185 uint16_t *stride_in_dw = rctx->streamout.stride_in_dw;
188 r600_flush_vgt_streamout(rctx);
190 for (i = 0; i < rctx->streamout.num_targets; i++) {
206 r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
211 if (rctx->family >= CHIP_RS780 && rctx->family <= CHIP_RV740) {
216 r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer),
220 if (rctx->streamout.append_bitmask & (1 << i) && t[i]->buf_filled_size_valid) {
233 r600_emit_reloc(rctx, &rctx->gfx, t[i]->buf_filled_size,
247 if (rctx->family > CHIP_R600 && rctx->family < CHIP_RV770) {
251 rctx->streamout.begin_emitted = true;
254 void r600_emit_streamout_end(struct r600_common_context *rctx)
256 struct radeon_cmdbuf *cs = &rctx->gfx.cs;
257 struct r600_so_target **t = rctx->streamout.targets;
261 r600_flush_vgt_streamout(rctx);
263 for (i = 0; i < rctx->streamout.num_targets; i++) {
277 r600_emit_reloc(rctx, &rctx->gfx, t[i]->buf_filled_size,
289 rctx->streamout.begin_emitted = false;
290 rctx->flags |= R600_CONTEXT_STREAMOUT_FLUSH;
300 static void r600_emit_streamout_enable(struct r600_common_context *rctx,
304 unsigned strmout_config_val = S_028B94_STREAMOUT_0_EN(r600_get_strmout_en(rctx));
306 unsigned strmout_buffer_val = rctx->streamout.hw_enabled_mask &
307 rctx->streamout.enabled_stream_buffers_mask;
309 if (rctx->gfx_level >= EVERGREEN) {
314 S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
315 S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
316 S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
318 radeon_set_context_reg(&rctx->gfx.cs, strmout_buffer_reg, strmout_buffer_val);
319 radeon_set_context_reg(&rctx->gfx.cs, strmout_config_reg, strmout_config_val);
322 static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable)
324 bool old_strmout_en = r600_get_strmout_en(rctx);
325 unsigned old_hw_enabled_mask = rctx->streamout.hw_enabled_mask;
327 rctx->streamout.streamout_enabled = enable;
329 rctx->streamout.hw_enabled_mask = rctx->streamout.enabled_mask |
330 (rctx->streamout.enabled_mask << 4) |
331 (rctx->streamout.enabled_mask << 8) |
332 (rctx->streamout.enabled_mask << 12);
334 if ((old_strmout_en != r600_get_strmout_en(rctx)) ||
335 (old_hw_enabled_mask != rctx->streamout.hw_enabled_mask)) {
336 rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
340 void r600_update_prims_generated_query_state(struct r600_common_context *rctx,
344 bool old_strmout_en = r600_get_strmout_en(rctx);
346 rctx->streamout.num_prims_gen_queries += diff;
347 assert(rctx->streamout.num_prims_gen_queries >= 0);
349 rctx->streamout.prims_gen_query_enabled =
350 rctx->streamout.num_prims_gen_queries != 0;
352 if (old_strmout_en != r600_get_strmout_en(rctx)) {
353 rctx->set_atom_dirty(rctx, &rctx->streamout.enable_atom, true);
358 void r600_streamout_init(struct r600_common_context *rctx)
360 rctx->b.create_stream_output_target = r600_create_so_target;
361 rctx->b.stream_output_target_destroy = r600_so_target_destroy;
362 rctx->streamout.begin_atom.emit = r600_emit_streamout_begin;
363 rctx->streamout.enable_atom.emit = r600_emit_streamout_enable;
364 rctx->streamout.enable_atom.num_dw = 6;