Lines Matching refs:rdst
2867 struct r600_texture *rdst = (struct r600_texture*)dst;
2872 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
2896 addr = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
2897 addr += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
2902 slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
2909 height = u_minify(rdst->resource.b.b.height0, dst_level);
2914 base = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
2929 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2936 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE);
2963 struct r600_texture *rdst = (struct r600_texture*)dst;
2982 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
2991 bpp = rdst->surface.bpe;
2992 dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
2995 dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
2998 dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
3021 dst_offset = (uint64_t)rdst->surface.u.legacy.level[dst_level].offset_256B * 256;
3022 dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;