Lines Matching refs:rctx
252 static void r600_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
254 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
323 struct r600_context *rctx = (struct r600_context *)ctx;
335 if (rctx->b.family > CHIP_R600)
392 if (rctx->b.family > CHIP_R600) {
464 struct r600_context *rctx = (struct r600_context *)ctx;
490 if (rctx->b.gfx_level == R700) {
514 S_028A4C_PS_ITER_SAMPLE(state->multisample && rctx->ps_iter_samples > 1);
515 if (rctx->b.family == CHIP_RV770) {
517 sc_mode_cntl |= S_028A4C_TILE_COVER_DISABLE(state->multisample && rctx->ps_iter_samples > 1);
519 if (rctx->b.gfx_level >= R700) {
566 if (rctx->b.gfx_level == R700) {
569 if (rctx->b.gfx_level == R600) {
796 static void r600_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
798 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
799 struct pipe_clip_state *state = &rctx->clip_state.state;
810 static void r600_init_color_surface(struct r600_context *rctx,
814 struct r600_screen *rscreen = rctx->screen;
827 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
883 format = r600_translate_colorformat(rctx->b.gfx_level, surf->base.format,
919 if (rctx->b.gfx_level == R600) {
988 if (!rctx->dummy_cmask ||
989 rctx->dummy_cmask->b.b.width0 < cmask.size ||
990 (1 << rctx->dummy_cmask->buf->alignment_log2) % cmask.alignment != 0) {
994 r600_resource_reference(&rctx->dummy_cmask, NULL);
995 rctx->dummy_cmask = (struct r600_resource*)
1000 if (unlikely(!rctx->dummy_cmask)) {
1006 ptr = pipe_buffer_map(&rctx->b.b, &rctx->dummy_cmask->b.b, PIPE_MAP_WRITE, &transfer);
1008 pipe_buffer_unmap(&rctx->b.b, transfer);
1010 r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask);
1013 if (!rctx->dummy_fmask ||
1014 rctx->dummy_fmask->b.b.width0 < fmask.size ||
1015 (1 << rctx->dummy_fmask->buf->alignment_log2) % fmask.alignment != 0) {
1016 r600_resource_reference(&rctx->dummy_fmask, NULL);
1017 rctx->dummy_fmask = (struct r600_resource*)
1022 if (unlikely(!rctx->dummy_fmask)) {
1027 r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask);
1042 static void r600_init_depth_surface(struct r600_context *rctx,
1091 struct r600_context *rctx = (struct r600_context *)ctx;
1101 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1110 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1112 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1113 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1115 rctx->framebuffer.compressed_cb_mask = 0;
1116 rctx->framebuffer.is_msaa_resolve = state->nr_cbufs == 2 &&
1120 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1125 bool force_cmask_fmask = rctx->b.gfx_level == R600 &&
1126 rctx->framebuffer.is_msaa_resolve &&
1139 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1147 rctx->framebuffer.export_16bpc = false;
1151 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1165 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1166 rctx->alphatest_state.bypass = alphatest_bypass;
1167 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1178 r600_init_depth_surface(rctx, surf);
1181 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1182 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1183 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1186 if (rctx->db_state.rsurf != surf) {
1187 rctx->db_state.rsurf = surf;
1188 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1189 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1191 } else if (rctx->db_state.rsurf) {
1192 rctx->db_state.rsurf = NULL;
1193 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1194 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1197 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
1198 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
1199 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
1200 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1201 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1204 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1205 rctx->alphatest_state.bypass = false;
1206 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1210 rctx->framebuffer.atom.num_dw =
1213 if (rctx->framebuffer.state.nr_cbufs) {
1214 rctx->framebuffer.atom.num_dw += 15 * rctx->framebuffer.state.nr_cbufs;
1215 rctx->framebuffer.atom.num_dw += 3 * (2 + rctx->framebuffer.state.nr_cbufs);
1217 if (rctx->framebuffer.state.zsbuf) {
1218 rctx->framebuffer.atom.num_dw += 16;
1220 rctx->framebuffer.atom.num_dw += 3;
1222 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770) {
1223 rctx->framebuffer.atom.num_dw += 2;
1226 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1228 r600_set_sample_locations_constant_buffer(rctx);
1229 rctx->framebuffer.do_update_surf_dirtiness = true;
1288 static void r600_emit_msaa_state(struct r600_context *rctx, int nr_samples)
1290 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1293 if (rctx->b.family == CHIP_R600) {
1355 static void r600_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1357 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1358 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1369 if (rctx->framebuffer.dual_src_blend && i == 1 && cb[0]) {
1387 reloc = radeon_add_to_buffer_list(&rctx->b,
1388 &rctx->b.gfx,
1400 reloc = radeon_add_to_buffer_list(&rctx->b,
1401 &rctx->b.gfx,
1413 reloc = radeon_add_to_buffer_list(&rctx->b,
1414 &rctx->b.gfx,
1443 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1452 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1453 &rctx->b.gfx,
1478 if (rctx->b.family > CHIP_R600 && rctx->b.family < CHIP_RV770 && sbu) {
1491 if (rctx->framebuffer.is_msaa_resolve) {
1501 r600_emit_msaa_state(rctx, rctx->framebuffer.nr_samples);
1506 struct r600_context *rctx = (struct r600_context *)ctx;
1508 if (rctx->ps_iter_samples == min_samples)
1511 rctx->ps_iter_samples = min_samples;
1512 if (rctx->framebuffer.nr_samples > 1) {
1513 r600_mark_atom_dirty(rctx, &rctx->rasterizer_state.atom);
1514 if (rctx->b.gfx_level == R600)
1515 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1519 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1521 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1526 if (rctx->b.gfx_level == R600) {
1549 static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
1551 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1561 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
1570 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1572 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1579 if (rctx->b.gfx_level >= R700) {
1594 if (rctx->b.num_occlusion_queries > 0 &&
1596 if (rctx->b.gfx_level >= R700) {
1604 if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface) {
1611 if (rctx->alphatest_state.sx_alpha_test_control) {
1617 if (rctx->b.gfx_level == R600 && rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0) {
1629 if (rctx->b.gfx_level == R600)
1632 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
1633 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
1645 if (rctx->b.family == CHIP_RV770 && a->log_samples == 3) {
1655 static void r600_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
1657 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1664 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1666 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1667 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1675 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1695 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1700 static void r600_emit_constant_buffers(struct r600_context *rctx,
1706 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1727 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1744 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1752 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1754 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
1760 static void r600_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1762 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
1768 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1770 r600_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
1776 static void r600_emit_sampler_views(struct r600_context *rctx,
1780 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1795 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
1807 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1809 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, R600_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS);
1812 static void r600_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1814 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views, R600_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS);
1817 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1819 r600_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, R600_FETCH_CONSTANTS_OFFSET_PS + R600_MAX_CONST_BUFFERS);
1822 static void r600_emit_sampler_states(struct r600_context *rctx,
1827 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1870 static void r600_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1872 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1875 static void r600_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1877 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36, R_00A800_TD_GS_SAMPLER0_BORDER_RED);
1880 static void r600_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
1882 r600_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1885 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1887 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1894 if (!rctx->seamless_cube_map.enabled) {
1900 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1905 radeon_set_context_reg(&rctx->b.gfx.cs, R_028C48_PA_SC_AA_MASK,
1909 static void r600_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
1911 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1920 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
1925 static void r600_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
1927 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1932 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
1940 if (rctx->gs_shader->gs_max_out_vertices <= 128)
1942 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
1944 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
1952 if (rctx->gs_shader->current->shader.gs_prim_id_input)
1960 static void r600_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
1962 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1974 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1983 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
1999 bool r600_adjust_gprs(struct r600_context *rctx)
2005 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
2014 def_gprs[i] = rctx->default_gprs[i];
2018 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2019 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2020 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2021 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
2023 num_gprs[R600_HW_STAGE_PS] = rctx->ps_shader->current->shader.bc.ngpr;
2024 if (rctx->gs_shader) {
2025 num_gprs[R600_HW_STAGE_ES] = rctx->vs_shader->current->shader.bc.ngpr;
2026 num_gprs[R600_HW_STAGE_GS] = rctx->gs_shader->current->shader.bc.ngpr;
2027 num_gprs[R600_HW_STAGE_VS] = rctx->gs_shader->current->gs_copy_shader->shader.bc.ngpr;
2031 num_gprs[R600_HW_STAGE_VS] = rctx->vs_shader->current->shader.bc.ngpr;
2081 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2082 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2083 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp2;
2084 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
2085 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
2090 void r600_init_atom_start_cs(struct r600_context *rctx)
2110 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2116 if (rctx->b.gfx_level == R600) {
2135 family = rctx->b.family;
2255 rctx->default_gprs[R600_HW_STAGE_PS] = num_ps_gprs;
2256 rctx->default_gprs[R600_HW_STAGE_VS] = num_vs_gprs;
2257 rctx->default_gprs[R600_HW_STAGE_GS] = 0;
2258 rctx->default_gprs[R600_HW_STAGE_ES] = 0;
2260 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2308 if (rctx->b.gfx_level >= R700) {
2389 if (rctx->b.gfx_level >= R700) {
2422 if (rctx->b.gfx_level == R700)
2424 if (rctx->b.gfx_level == R700 && rctx->screen->b.has_streamout)
2428 if (rctx->screen->b.has_streamout) {
2439 struct r600_context *rctx = (struct r600_context *)ctx;
2448 /* Pull any state we use out of rctx. Make sure that any additional
2452 bool sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
2453 bool flatshade = rctx->rasterizer ? rctx->rasterizer->flatshade : 0;
2454 bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0;
2561 if (rctx->b.family == CHIP_R600)
2659 struct r600_context *rctx = (struct r600_context *)ctx;
2668 switch (rctx->b.family) {
2688 if (rctx->b.gfx_level >= R700) {
2735 void *r600_create_resolve_blend(struct r600_context *rctx)
2752 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2755 void *r700_create_resolve_blend(struct r600_context *rctx)
2762 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2765 void *r600_create_decompress_blend(struct r600_context *rctx)
2772 return r600_create_blend_state_mode(&rctx->b.b, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2775 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2780 if (rctx->b.family == CHIP_RV610 || rctx->b.family == CHIP_RV630 ||
2781 rctx->b.family == CHIP_RV620 || rctx->b.family == CHIP_RV635)
2796 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
2799 void r600_update_db_shader_control(struct r600_context * rctx)
2805 if (!rctx->ps_shader) {
2809 dual_export = rctx->framebuffer.export_16bpc &&
2810 !rctx->ps_shader->current->ps_depth_export;
2812 db_shader_control = rctx->ps_shader->current->db_shader_control |
2815 ps_conservative_z = rctx->ps_shader->current->shader.ps_conservative_z;
2824 if (rctx->alphatest_state.sx_alpha_test_control) {
2830 if (db_shader_control != rctx->db_misc_state.db_shader_control ||
2831 ps_conservative_z != rctx->db_misc_state.ps_conservative_z) {
2832 rctx->db_misc_state.db_shader_control = db_shader_control;
2833 rctx->db_misc_state.ps_conservative_z = ps_conservative_z;
2834 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
2850 static boolean r600_dma_copy_tile(struct r600_context *rctx,
2865 struct radeon_cmdbuf *cs = &rctx->b.dma.cs;
2929 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2935 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ);
2936 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE);
2961 struct r600_context *rctx = (struct r600_context *)ctx;
2969 if (rctx->b.dma.cs.priv == NULL) {
2977 r600_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
2982 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3029 r600_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset, size);
3031 if (!r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3044 void r600_init_state_functions(struct r600_context *rctx)
3058 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, r600_emit_framebuffer_state, 0);
3061 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, r600_emit_vs_constant_buffers, 0);
3062 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, r600_emit_gs_constant_buffers, 0);
3063 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, r600_emit_ps_constant_buffers, 0);
3068 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, r600_emit_vs_sampler_states, 0);
3069 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, r600_emit_gs_sampler_states, 0);
3070 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, r600_emit_ps_sampler_states, 0);
3072 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, r600_emit_vs_sampler_views, 0);
3073 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, r600_emit_gs_sampler_views, 0);
3074 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, r600_emit_ps_sampler_views, 0);
3075 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, r600_emit_vertex_buffers, 0);
3077 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
3079 r600_init_atom(rctx, &rctx->seamless_cube_map.atom, id++, r600_emit_seamless_cube_map, 3);
3080 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, r600_emit_sample_mask, 3);
3081 rctx->sample_mask.sample_mask = ~0;
3083 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
3084 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
3085 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
3086 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, r600_emit_cb_misc_state, 7);
3087 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6);
3088 r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26);
3089 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 7);
3090 r600_init_atom(rctx, &rctx->db_state.atom, id++, r600_emit_db_state, 11);
3091 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
3092 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 9);
3093 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
3094 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
3095 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
3096 r600_init_atom(rctx, &rctx->config_state.atom, id++, r600_emit_config_state, 3);
3097 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
3098 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, r600_emit_vertex_fetch_shader, 5);
3099 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
3100 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
3101 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
3103 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
3104 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, r600_emit_shader_stages, 0);
3105 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, r600_emit_gs_rings, 0);
3107 rctx->b.b.create_blend_state = r600_create_blend_state;
3108 rctx->b.b.create_depth_stencil_alpha_state = r600_create_dsa_state;
3109 rctx->b.b.create_rasterizer_state = r600_create_rs_state;
3110 rctx->b.b.create_sampler_state = r600_create_sampler_state;
3111 rctx->b.b.create_sampler_view = r600_create_sampler_view;
3112 rctx->b.b.set_framebuffer_state = r600_set_framebuffer_state;
3113 rctx->b.b.set_polygon_stipple = r600_set_polygon_stipple;
3114 rctx->b.b.set_min_samples = r600_set_min_samples;
3115 rctx->b.b.get_sample_position = r600_get_sample_position;
3116 rctx->b.dma_copy = r600_dma_copy;