Lines Matching defs:tmp
465 unsigned tmp, sc_mode_cntl, spi_interp;
539 tmp = r600_pack_float_12p4(state->point_size/2);
541 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
632 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
642 view->tex_resource = &tmp->resource;
672 struct r600_texture *tmp = (struct r600_texture*)texture;
699 do_endian_swap = !tmp->db_compatible;
716 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
721 tmp = tmp->flushed_depth_texture;
731 pitch = tmp->surface.u.legacy.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
741 switch (tmp->surface.u.legacy.level[offset_level].mode) {
754 view->tex_resource = &tmp->resource;
757 S_038000_TILE_TYPE(tmp->non_disp_tiling) |
763 view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset_256B;
764 if (offset_level >= tmp->resource.b.b.last_level) {
765 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset_256B;
767 view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset_256B;
1888 unsigned tmp;
1890 tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1895 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1897 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2007 unsigned tmp, tmp2;
2075 tmp = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
2081 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2082 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
2111 uint32_t tmp, i;
2263 tmp = 0;
2272 tmp |= S_008C00_VC_ENABLE(1);
2275 tmp |= S_008C00_DX9_CONSTS(0);
2276 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2277 tmp |= S_008C00_PS_PRIO(ps_prio);
2278 tmp |= S_008C00_VS_PRIO(vs_prio);
2279 tmp |= S_008C00_GS_PRIO(gs_prio);
2280 tmp |= S_008C00_ES_PRIO(es_prio);
2281 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2284 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2285 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2287 r600_store_value(cb, tmp);
2290 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2291 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2292 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2293 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2294 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2297 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2298 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2299 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2302 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2303 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2304 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2444 unsigned tmp, sid, ufi = 0;
2473 tmp = S_028644_SEMANTIC(sid);
2477 tmp |= S_028644_DEFAULT_VAL(3);
2482 tmp |= S_028644_FLAT_SHADE(1);
2487 tmp |= S_028644_PT_SPRITE_TEX(1);
2491 tmp |= S_028644_SEL_CENTROID(1);
2494 tmp |= S_028644_SEL_SAMPLE(1);
2498 tmp |= S_028644_SEL_LINEAR(1);
2501 r600_store_value(cb, tmp);
2600 unsigned i, tmp, nparams = 0;
2604 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2605 spi_vs_out_id[nparams / 4] |= tmp;