Lines Matching defs:surf
811 struct r600_surface *surf,
815 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
816 unsigned level = surf->base.u.tex.level;
827 r600_init_flushed_depth_texture(&rctx->b.b, surf->base.texture, NULL);
833 color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
834 S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
855 desc = util_format_description(surf->base.format);
883 format = r600_translate_colorformat(rctx->b.gfx_level, surf->base.format,
887 swap = r600_translate_colorswap(surf->base.format, do_endian_swap);
906 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
934 surf->export_16bpc = true;
948 surf->export_16bpc = true;
953 surf->cb_color_base = offset >> 8;
954 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
956 surf->cb_color_fmask = surf->cb_color_base;
957 surf->cb_color_cmask = surf->cb_color_base;
958 surf->cb_color_mask = 0;
960 r600_resource_reference(&surf->cb_buffer_cmask, &rtex->resource);
961 r600_resource_reference(&surf->cb_buffer_fmask, &rtex->resource);
964 surf->cb_color_cmask = rtex->cmask.offset >> 8;
965 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max);
969 surf->cb_color_fmask = rtex->fmask.offset >> 8;
970 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(rtex->fmask.slice_tile_max);
1001 surf->color_initialized = false;
1010 r600_resource_reference(&surf->cb_buffer_cmask, rctx->dummy_cmask);
1023 surf->color_initialized = false;
1027 r600_resource_reference(&surf->cb_buffer_fmask, rctx->dummy_fmask);
1031 surf->cb_color_cmask = 0;
1032 surf->cb_color_fmask = 0;
1033 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1037 surf->cb_color_info = color_info;
1038 surf->cb_color_view = color_view;
1039 surf->color_initialized = true;
1043 struct r600_surface *surf)
1045 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1048 level = surf->base.u.tex.level;
1066 format = r600_translate_dbformat(surf->base.format);
1069 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1070 surf->db_depth_base = offset >> 8;
1071 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1072 S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1073 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1074 surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1;
1077 surf->db_htile_data_base = rtex->htile_offset >> 8;
1078 surf->db_htile_surface = S_028D24_HTILE_WIDTH(1) |
1082 surf->db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1);
1085 surf->depth_initialized = true;
1092 struct r600_surface *surf;
1129 surf = (struct r600_surface*)state->cbufs[i];
1130 if (!surf)
1133 rtex = (struct r600_texture*)surf->base.texture;
1138 if (!surf->color_initialized || force_cmask_fmask) {
1139 r600_init_color_surface(rctx, surf, force_cmask_fmask);
1142 surf->color_initialized = false;
1146 if (!surf->export_16bpc) {
1160 surf = (struct r600_surface*)state->cbufs[0];
1161 if (surf) {
1162 alphatest_bypass = surf->alphatest_bypass;
1173 surf = (struct r600_surface*)state->zsbuf;
1177 if (!surf->depth_initialized) {
1178 r600_init_depth_surface(rctx, surf);
1186 if (rctx->db_state.rsurf != surf) {
1187 rctx->db_state.rsurf = surf;
1451 struct r600_surface *surf = (struct r600_surface*)state->zsbuf;
1456 (surf->base.texture->nr_samples > 1 ?
1461 radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE */
1462 radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW */
1464 radeon_emit(cs, surf->db_depth_base); /* R_02800C_DB_DEPTH_BASE */
1465 radeon_emit(cs, surf->db_depth_info); /* R_028010_DB_DEPTH_INFO */
1470 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);