Lines Matching defs:rsrc
2866 struct r600_texture *rsrc = (struct r600_texture*)src;
2873 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
2883 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
2890 height = u_minify(rsrc->resource.b.b.height0, src_level);
2895 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
2915 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
2916 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
2929 r600_need_dma_space(&rctx->b, ncopy * 7, &rdst->resource, &rsrc->resource);
2935 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource, RADEON_USAGE_READ);
2962 struct r600_texture *rsrc = (struct r600_texture*)src;
2983 dstz, rsrc, src_level, src_box))
2993 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
2994 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
2996 copy_height = src_box->height / rsrc->surface.blk_h;
2999 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3018 src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
3019 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;