Lines Matching defs:offset
496 /* offset */
635 uint64_t offset = view->base.u.buf.offset;
645 view->tex_resource_words[0] = offset;
647 view->tex_resource_words[2] = S_038008_BASE_ADDRESS_HI(offset >> 32UL) |
821 unsigned offset;
832 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
953 surf->cb_color_base = offset >> 8;
964 surf->cb_color_cmask = rtex->cmask.offset >> 8;
969 surf->cb_color_fmask = rtex->fmask.offset >> 8;
1046 unsigned level, pitch, slice, format, offset, array_mode;
1049 offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
1070 surf->db_depth_base = offset >> 8;
1254 int offset, index;
1264 offset = 4 * (sample_index * 2);
1265 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1267 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1271 offset = 4 * (sample_index * 2);
1272 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1274 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1278 offset = 4 * (sample_index % 4 * 2);
1280 val.idx = (sample_locs_8x[index] >> offset) & 0xf;
1282 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf;
1672 unsigned offset;
1679 offset = vb->buffer_offset;
1684 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1685 radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* RESOURCEi_WORD1 */
1712 unsigned offset;
1719 offset = cb->buffer_offset;
1725 radeon_set_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1733 radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
1859 unsigned offset;
1861 offset = border_color_reg;
1862 offset += i * 16;
1863 radeon_set_config_reg_seq(cs, offset, 4);
1918 radeon_set_context_reg(cs, R_028894_SQ_PGM_START_FS, shader->offset >> 8);