Lines Matching refs:index
601 /* work out gpr and base_chan from index */
674 * USE_VTX_RENDER_TARGET_INDX - render target index in the Z channel of export 61
675 * USE_VTX_VIEWPORT_INDX - viewport index in the W channel of export 61
677 * exclusive from render target index)
696 /* Map name/sid pair from tgsi to the 8-bit semantic index for SPI setup */
699 int index, name = io->name;
709 index = 0;
713 index = 9 + io->sid;
715 index = io->sid;
718 index = 0x80 | (name<<3) | (io->sid);
724 index++;
727 return index;
730 /* we need this to get a common lds index for vs/tcs/tes input/outputs */
731 int r600_get_lds_unique_index(unsigned semantic_name, unsigned index)
739 assert(index <= 1);
740 return 2 + index;
742 return 4 + index;
744 return 12 + index;
746 return 14 + index;
750 if (index <= 63-17)
751 return 17 + index;
764 return 2 + index;
777 static int evergreen_interp_input(struct r600_shader_ctx *ctx, int index)
781 if (ctx->shader->input[index].spi_sid) {
782 ctx->shader->input[index].lds_pos = ctx->shader->nlds++;
783 if (ctx->shader->input[index].interpolate > 0) {
784 evergreen_interp_assign_ij_index(ctx, index);
785 r = evergreen_interp_alu(ctx, index);
787 r = evergreen_interp_flat(ctx, index);
939 static inline int get_address_file_reg(struct r600_shader_ctx *ctx, int index)
941 return index > 0 ? ctx->bc->index_reg[index - 1] : ctx->bc->ar_reg;
1031 /* vec4 index into spilled scratch memory */
1049 /* regular GPR index, minus the holes from spilled arrays */
1710 int index;
1715 index = tgsi_src->Register.Index * 4 + tgsi_src->Register.SwizzleX;
1716 r600_bytecode_special_constants(ctx->literals[index], &r600_src->sel);
1720 index = tgsi_src->Register.Index;
1722 memcpy(r600_src->value, ctx->literals + index * 4, sizeof(r600_src->value));
1881 unsigned index = src->Register.Index;
1911 we have to put the R0.x/y/w into Rt.x Rt+1.x Rt+2.x then index reg from Rt.
1967 index = src->Register.Index - first;
1975 vtx.offset = index * 16; /*bytes*/
2048 ubyte *name, *index, *array_first;
2093 index = info->input_semantic_index;
2097 index = info->output_semantic_index;
2124 index[first]);
2128 index[reg.Register.Index]);
2934 * single vertex data, gs_next_vertex - current vertex index */
3275 /* TF_WRITE takes index in R.x, value in R.y */
3370 * operations, which store the returned value to an index
3372 * The index is calculated by taking the thread id,
7393 unsigned index)
7396 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
7397 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
7398 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
7399 ctx->src[index].neg || ctx->src[index].abs ||
7400 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
7404 unsigned index)
7407 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
7823 /* Evaluate the array index according to floor(idx + 0.5). This
7825 * otherwise the fractional part of the array index will interfere
7838 /* Because the array slice index and the cube face index are merged
7839 * into one value we have to make sure the array slice index is >= 0,
8258 /* Obtain the sample index for reading a compressed MSAA color texture.
8265 * Assume src.z contains the sample index. It should be modified like this:
8411 /* make sure array index selector is 0, this is just a safety
8580 /* the array index is read from Y */
8584 /* the array index is read from Z */
8596 /* the array index is read from Z, coordinate will be corrected elsewhere */
8600 * evaluate the array index */
8659 uint32_t index = src->Register.Index;
8663 if (index > ctx->shader->atomics[i].end)
8665 if (index < ctx->shader->atomics[i].start)
8667 uint32_t offset = (index - ctx->shader->atomics[i].start);