Lines Matching defs:inst
1317 const struct tgsi_full_instruction *inst = &parse.FullToken.FullInstruction;
1318 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE ||
1319 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
1320 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_CENTROID)
1324 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
1326 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
1333 interpolate = ctx->info.input_interpolate[inst->Src[0].Register.Index];
1996 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
1999 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2000 struct tgsi_full_src_register *src = &inst->Src[i];
2286 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2289 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
2290 struct tgsi_full_src_register *src = &inst->Src[i];
2316 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2320 for (i = 0, nconst = 0; i < inst->Instruction.NumSrcRegs; i++) {
2321 if (inst->Src[i].Register.File == TGSI_FILE_CONSTANT) {
2324 tgsi_src(ctx, &inst->Src[i], &ctx->src[i]);
2326 for (i = 0, j = nconst - 1; i < inst->Instruction.NumSrcRegs; i++) {
2327 if (inst->Src[i].Register.File != TGSI_FILE_CONSTANT) {
2332 int chan = inst->Src[i].Indirect.Swizzle;
2372 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
2376 for (i = 0, nliteral = 0; i < inst->Instruction.NumSrcRegs; i++) {
2381 for (i = 0, j = nliteral - 1; i < inst->Instruction.NumSrcRegs; i++) {
3115 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
3116 const struct tgsi_full_dst_register *dst = &inst->Dst[0];
3122 if (inst->Dst[0].Register.File != TGSI_FILE_OUTPUT)
3131 &inst->Dst[0], NULL, ctx->tess_output_info, 1);
4428 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4468 if (inst->Instruction.Saturate) {
4479 cf.comp_mask = inst->Dst[0].Register.WriteMask;
4511 if (inst->Instruction.Saturate) {
4526 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4527 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4531 int swizzle_x = inst->Src[0].Register.SwizzleX;
4584 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4589 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4595 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4622 write_mask = inst->Dst[0].Register.WriteMask;
4638 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4653 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4654 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4676 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4686 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4690 if (inst->Dst[0].Register.WriteMask & (1 << i))
4691 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4709 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4711 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4739 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4743 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4767 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4797 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4800 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4804 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4813 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4828 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4831 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
4835 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
4844 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4859 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4861 unsigned write_mask = inst->Dst[0].Register.WriteMask;
4871 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
4893 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
4902 if (inst->Dst[1].Register.WriteMask & (1 << i)) {
4909 tgsi_dst(ctx, &inst->Dst[1], i, &alu.dst);
4923 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
4926 int write_mask = inst->Dst[0].Register.WriteMask;
4929 assert(inst->Instruction.Opcode == TGSI_OPCODE_I2D ||
4930 inst->Instruction.Opcode == TGSI_OPCODE_U2D);
5020 tgsi_dst(ctx, &inst->Dst[0], dchan + i, &alu.dst);
5035 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5038 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5040 assert(inst->Instruction.Opcode == TGSI_OPCODE_D2I ||
5041 inst->Instruction.Opcode == TGSI_OPCODE_D2U);
5049 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5056 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5104 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5107 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5111 assert(inst->Instruction.NumSrcRegs == 1);
5114 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
5115 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
5126 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5132 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5145 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5148 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5153 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5157 if (inst->Instruction.Opcode == TGSI_OPCODE_RSQ) {
5161 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5162 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5175 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5178 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5182 if (!(inst->Dst[0].Register.WriteMask & (1 << k)))
5188 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5203 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5209 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5224 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5227 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5232 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
5233 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
5235 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
5240 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
5254 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5260 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5277 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5285 assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
5286 inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
5288 k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
5318 tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
5407 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5409 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5422 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5423 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5438 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5441 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
5462 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
5469 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5481 const struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5493 if (inst->Instruction.Opcode == TGSI_OPCODE_KILL) {
5515 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5535 if (inst->Dst[0].Register.WriteMask & (1 << 2))
5601 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5617 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
5630 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
5631 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 0) & 1;
5642 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
5643 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 1) & 1;
5653 tgsi_dst(ctx, &inst->Dst[0], 3, &alu.dst);
5654 alu.dst.write = (inst->Dst[0].Register.WriteMask >> 3) & 1;
5665 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5673 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5689 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5698 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5699 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5711 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5717 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
5732 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5735 int last_slot = (inst->Dst[0].Register.WriteMask & 0x8) ? 4 : 3;
5769 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
5770 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
5846 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
5849 unsigned write_mask = inst->Dst[0].Register.WriteMask;
5858 if (inst->Src[0].Register.Index == inst->Dst[0].Register.Index ||
5859 inst->Src[1].Register.Index == inst->Dst[0].Register.Index) {
6482 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6530 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6572 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6596 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6633 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6636 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6665 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6682 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6685 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6720 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6738 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6741 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6778 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6801 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6802 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6836 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6859 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6863 unsigned write_mask = inst->Dst[0].Register.WriteMask;
6936 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6962 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
6977 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
6981 unsigned write_mask = inst->Dst[0].Register.WriteMask;
7041 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7063 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7067 const int input = inst->Src[0].Register.Index + ctx->shader->nsys_inputs;
7069 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
7072 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
7073 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7088 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
7089 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7094 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7127 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7151 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7184 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
7185 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
7204 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7206 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7213 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7225 static int tgsi_helper_copy(struct r600_shader_ctx *ctx, struct tgsi_full_instruction *inst)
7232 if (!(inst->Dst[0].Register.WriteMask & (1 << i))) {
7237 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7294 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7298 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7305 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7306 r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
7313 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7318 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7323 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7347 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7358 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
7362 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
7364 alu.dst.write = (inst->Dst[0].Register.WriteMask >> i) & 1;
7366 switch (inst->Instruction.Opcode) {
7395 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7396 return (inst->Src[index].Register.File != TGSI_FILE_TEMPORARY &&
7397 inst->Src[index].Register.File != TGSI_FILE_INPUT &&
7398 inst->Src[index].Register.File != TGSI_FILE_OUTPUT) ||
7400 (inst->Src[index].Register.File == TGSI_FILE_INPUT && ctx->type == PIPE_SHADER_GEOMETRY);
7406 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7407 return ctx->file_offset[inst->Src[index].Register.File] + inst->Src[index].Register.Index;
7414 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7417 int sampler_index_mode = inst->Src[1].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7443 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7444 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
7445 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
7446 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
7447 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
7458 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
7459 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
7484 if (inst->Dst[0].Register.WriteMask & 3) {
7509 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7512 int sampler_index_mode = inst->Src[reg_idx].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7523 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
7537 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
7538 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
7539 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 4 : 7; /* SEL_Y */
7540 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 4 : 7; /* SEL_Z */
7541 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 4 : 7; /* SEL_W */
7554 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
7562 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7563 (inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
7564 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
7566 bool txf_add_offsets = inst->Texture.NumOffsets &&
7567 inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
7568 inst->Texture.Texture != TGSI_TEXTURE_BUFFER;
7572 const boolean src_requires_loading = (inst->Instruction.Opcode != TGSI_OPCODE_TXQS &&
7583 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
7584 ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7585 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
7586 if (inst->Dst[0].Register.WriteMask & 4) {
7591 if (inst->Instruction.Opcode == TGSI_OPCODE_TEX2 ||
7592 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7593 inst->Instruction.Opcode == TGSI_OPCODE_TXL2 ||
7594 inst->Instruction.Opcode == TGSI_OPCODE_TG4)
7598 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD)
7601 sampler_index_mode = inst->Src[sampler_src_reg].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
7605 if (inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
7606 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
7611 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
7618 if (inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
7683 if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
7684 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7685 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7686 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
7687 inst->Instruction.Opcode != TGSI_OPCODE_TXQ) {
7790 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
7791 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7794 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
7807 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
7808 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
7906 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB ||
7907 inst->Instruction.Opcode == TGSI_OPCODE_TXL ||
7908 inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7909 inst->Instruction.Opcode == TGSI_OPCODE_TXL2) {
7912 if (inst->Instruction.Opcode == TGSI_OPCODE_TXB2 ||
7913 inst->Instruction.Opcode == TGSI_OPCODE_TXL2)
7930 if (inst->Instruction.Opcode == TGSI_OPCODE_TXD) {
7982 if (inst->Texture.Texture != TGSI_TEXTURE_RECT) {
7991 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
8001 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
8002 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
8006 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
8007 inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
8008 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) && !src_loaded) {
8009 int end = inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ? 3 : 2;
8024 if (inst->Texture.Texture == TGSI_TEXTURE_RECT ||
8025 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
8172 if (inst->Texture.NumOffsets) {
8173 assert(inst->Texture.NumOffsets == 1);
8178 const struct tgsi_texture_offset *off = inst->TexOffsets;
8180 switch (inst->Texture.Texture) {
8237 switch (inst->Texture.Texture) {
8239 offset_z = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleZ] << 1;
8247 offset_y = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleY] << 1;
8253 offset_x = ctx->literals[4 * inst->TexOffsets[0].Index + inst->TexOffsets[0].SwizzleX] << 1;
8349 alu.dst.sel = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8379 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
8385 inst->Dst[0].Register.WriteMask &= ~4;
8390 inst->TexOffsets[0].File != TGSI_FILE_NULL &&
8391 inst->TexOffsets[0].File != TGSI_FILE_IMMEDIATE) {
8406 t->src_gpr = ctx->file_offset[inst->TexOffsets[0].File] + inst->TexOffsets[0].Index;
8407 t->src_sel_x = inst->TexOffsets[0].SwizzleX;
8408 t->src_sel_y = inst->TexOffsets[0].SwizzleY;
8409 if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
8410 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)
8415 t->src_sel_z = inst->TexOffsets[0].SwizzleZ;
8425 if (inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
8426 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
8427 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
8428 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
8429 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY ||
8430 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY ||
8431 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
8463 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8465 if (inst->Instruction.Opcode == TGSI_OPCODE_DDX_FINE ||
8466 inst->Instruction.Opcode == TGSI_OPCODE_DDY_FINE) {
8470 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4) {
8471 if (inst->Src[1].Register.File != TGSI_FILE_IMMEDIATE) {
8477 assert(inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY);
8480 int8_t texture_component_select = ctx->literals[4 * inst->Src[1].Register.Index + inst->Src[1].Register.SwizzleX];
8485 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8486 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8487 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8488 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8491 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 1 : 7;
8492 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 2 : 7;
8493 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 0 : 7;
8494 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8497 else if (inst->Instruction.Opcode == TGSI_OPCODE_LODQ) {
8498 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8499 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8503 else if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
8510 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
8511 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
8512 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
8513 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
8517 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQS) {
8535 if (inst->Texture.Texture == TGSI_TEXTURE_CUBE ||
8536 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE ||
8537 inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
8538 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
8545 if (inst->Texture.Texture != TGSI_TEXTURE_RECT &&
8546 inst->Texture.Texture != TGSI_TEXTURE_SHADOWRECT) {
8555 if (inst->Instruction.Opcode == TGSI_OPCODE_TG4 &&
8556 (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
8557 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY)) {
8567 if ((inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D ||
8568 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D ||
8569 inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT ||
8570 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) &&
8576 if (inst->Texture.Texture == TGSI_TEXTURE_1D_ARRAY ||
8577 inst->Texture.Texture == TGSI_TEXTURE_SHADOW1D_ARRAY) {
8589 } else if (inst->Texture.Texture == TGSI_TEXTURE_2D_ARRAY ||
8590 inst->Texture.Texture == TGSI_TEXTURE_SHADOW2D_ARRAY) {
8593 } else if ((inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
8594 inst->Texture.Texture == TGSI_TEXTURE_SHADOWCUBE_ARRAY) &&
8621 switch (inst->Texture.Texture) {
8677 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8682 uav_id = find_hw_atomic_counter(ctx, &inst->Src[0]);
8684 if (inst->Src[0].Register.Indirect) {
8689 alu.src[0].sel = get_address_file_reg(ctx, inst->Src[0].Indirect.Index);
8724 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8737 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8761 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8773 switch (inst->Memory.Texture) {
8819 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8821 if (inst->Src[src_idx].Register.File == TGSI_FILE_IMMEDIATE) {
8822 int value = (ctx->literals[4 * inst->Src[src_idx].Register.Index + inst->Src[src_idx].Register.SwizzleX]);
8862 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8868 unsigned rat_index_mode = tgsi_indirect_to_rat_index_mode(inst->Src[0].Indirect);
8879 vtx.buffer_id = inst->Src[0].Register.Index + base;
8884 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8885 vtx.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7; /* SEL_X */
8886 vtx.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7; /* SEL_Y */
8887 vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7; /* SEL_Z */
8888 vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7; /* SEL_W */
8893 if (inst->Dst[0].Register.WriteMask & 8) {
8896 } else if (inst->Dst[0].Register.WriteMask & 4) {
8899 } else if (inst->Dst[0].Register.WriteMask & 2) {
8917 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
8925 unsigned rat_index_mode = tgsi_indirect_to_rat_index_mode(inst->Src[0].Indirect);
8939 cf->rat.id = ctx->shader->rat_base + inst->Src[0].Register.Index;
8940 cf->rat.inst = V_RAT_INST_NOP_RTN;
8955 desc = util_format_description(inst->Memory.Format);
8956 r600_vertex_data_type(inst->Memory.Format,
8960 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
8965 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
8987 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9003 ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index, inst->Dst[0].Register.WriteMask);
9011 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9012 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
9014 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
9016 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
9018 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
9025 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9028 unsigned rat_index_mode = tgsi_indirect_to_rat_index_mode(inst->Dst[0].Indirect);
9054 lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9057 if (!((1 << i) & inst->Dst[0].Register.WriteMask))
9082 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index + ctx->info.file_count[TGSI_FILE_IMAGE];
9083 cf->rat.inst = V_RAT_INST_STORE_TYPED;
9107 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9112 unsigned rat_index_mode = tgsi_indirect_to_rat_index_mode(inst->Dst[0].Indirect);
9118 if (inst->Src[1].Register.File != TGSI_FILE_TEMPORARY)
9146 cf->rat.id = ctx->shader->rat_base + inst->Dst[0].Register.Index;
9147 cf->rat.inst = V_RAT_INST_STORE_TYPED;
9166 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9169 int write_mask = inst->Dst[0].Register.WriteMask;
9235 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9236 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER)
9238 else if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY)
9246 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9255 unsigned rat_index_mode = tgsi_indirect_to_rat_index_mode(inst->Src[0].Indirect);
9262 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
9319 cf->rat.id = rat_base + inst->Src[0].Register.Index;
9320 cf->rat.inst = ctx->inst_info->op;
9336 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
9337 desc = util_format_description(inst->Memory.Format);
9338 r600_vertex_data_type(inst->Memory.Format,
9349 vtx.buffer_id = immed_base + inst->Src[0].Register.Index;
9354 vtx.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9405 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9408 int gds_op = get_gds_op(inst->Instruction.Opcode);
9415 fprintf(stderr, "unknown GDS op for opcode %d\n", inst->Instruction.Opcode);
9424 if (inst->Src[3].Register.File == TGSI_FILE_IMMEDIATE) {
9425 int value = (ctx->literals[4 * inst->Src[3].Register.Index + inst->Src[3].Register.SwizzleX]);
9450 if (inst->Src[2].Register.File == TGSI_FILE_IMMEDIATE) {
9451 int value = (ctx->literals[4 * inst->Src[2].Register.Index + inst->Src[2].Register.SwizzleX]);
9482 gds.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9536 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9537 int lds_op = get_lds_op(inst->Instruction.Opcode);
9561 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
9573 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9574 if (inst->Src[0].Register.File == TGSI_FILE_IMAGE)
9576 if (inst->Src[0].Register.File == TGSI_FILE_HW_ATOMIC)
9578 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
9580 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY)
9587 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9593 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
9594 (inst->Src[0].Register.File == TGSI_FILE_IMAGE && inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
9599 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER)
9604 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY &&
9605 inst->Dst[0].Register.WriteMask & 4) {
9610 sampler_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // CF_INDEX_1 : CF_INDEX_NONE
9628 tgsi_dst(ctx, &inst->Dst[0], 2, &alu.dst);
9634 inst->Dst[0].Register.WriteMask &= ~4;
9638 tex.sampler_id = R600_IMAGE_REAL_RESOURCE_OFFSET + inst->Src[0].Register.Index;
9646 tex.dst_sel_x = (inst->Dst[0].Register.WriteMask & 1) ? 0 : 7;
9647 tex.dst_sel_y = (inst->Dst[0].Register.WriteMask & 2) ? 1 : 7;
9648 tex.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
9649 tex.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
9650 tex.dst_gpr = ctx->file_offset[inst->Dst[0].Register.File] + inst->Dst[0].Register.Index;
9660 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9662 unsigned lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9670 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9678 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9692 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9714 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9736 r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
9743 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9754 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9768 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9771 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9784 for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
9785 r = tgsi_make_src_for_op3(ctx, inst->Dst[0].Register.WriteMask,
9792 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9801 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9816 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9819 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
9822 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
9830 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9845 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9851 if (inst->Dst[0].Register.WriteMask & 1) {
9895 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
9903 r = tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
9918 if ((inst->Dst[0].Register.WriteMask >> 2) & 0x1) {
9954 if ((inst->Dst[0].Register.WriteMask >> 3) & 0x1) {
9969 return tgsi_helper_copy(ctx, inst);
9974 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
9980 if (inst->Dst[0].Register.WriteMask & 1) {
10031 if ((inst->Dst[0].Register.WriteMask >> 1) & 1) {
10173 if ((inst->Dst[0].Register.WriteMask >> 2) & 1) {
10212 if ((inst->Dst[0].Register.WriteMask >> 3) & 1) {
10229 return tgsi_helper_copy(ctx, inst);
10234 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10237 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10238 unsigned reg = get_address_file_reg(ctx, inst->Dst[0].Register.Index);
10240 assert(inst->Dst[0].Register.Index < 3);
10243 switch (inst->Instruction.Opcode) {
10259 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10271 if (inst->Dst[0].Register.Index > 0)
10272 ctx->bc->index_loaded[inst->Dst[0].Register.Index - 1] = 0;
10280 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10283 int i, lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10285 switch (inst->Instruction.Opcode) {
10292 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10323 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10337 if (inst->Dst[0].Register.WriteMask & (1 << i)) {
10357 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10365 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10783 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10784 int stream = ctx->literals[inst->Src[0].Register.Index * 4 + inst->Src[0].Register.SwizzleX];
10801 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10804 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10808 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10830 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10834 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10854 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10857 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10878 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10884 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10902 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10905 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10935 if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
10938 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
10953 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
10955 int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
10959 if ((inst->Src[0].Register.File == inst->Dst[0].Register.File &&
10960 inst->Src[0].Register.Index == inst->Dst[0].Register.Index) ||
10961 (inst->Src[2].Register.File == inst->Dst[0].Register.File &&
10962 inst->Src[2].Register.Index == inst->Dst[0].Register.Index))
10992 tgsi_dst(ctx, &inst->Dst[0], i, &alu.dst);
11012 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11018 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11025 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
11109 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11158 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
11169 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11182 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11228 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
11239 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11255 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11341 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11351 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
11413 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11421 if (inst->Dst[0].Register.WriteMask != 0x3)
11719 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
11728 tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
11740 struct tgsi_full_instruction *inst = &ctx->parse.FullToken.FullInstruction;
11770 tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);