Lines Matching refs:ctx
410 struct pipe_context *ctx = rquery->b.flushed ? NULL : &rctx->b;
412 result->b = screen->fence_finish(screen, ctx, query->fence,
577 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
581 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
700 struct r600_context *ctx = (struct r600_context*)rctx;
701 r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom);
726 static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
731 struct radeon_cmdbuf *cs = &ctx->gfx.cs;
756 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
769 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE |
773 static void r600_query_hw_emit_start(struct r600_common_context *ctx,
781 r600_update_occlusion_query_state(ctx, query->b.type, 1);
782 r600_update_prims_generated_query_state(ctx, query->b.type, 1);
784 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_begin + query->num_cs_dw_end,
793 query->buffer.buf = r600_new_query_buffer(ctx->screen, query);
801 query->ops->emit_start(ctx, query, query->buffer.buf, va);
803 ctx->num_cs_dw_queries_suspend += query->num_cs_dw_end;
806 static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
811 struct radeon_cmdbuf *cs = &ctx->gfx.cs;
824 fence_va = va + ctx->screen->info.max_render_backends * 16 - 8;
842 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
862 r600_emit_reloc(ctx, &ctx->gfx, query->buffer.buf, RADEON_USAGE_WRITE |
866 r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
872 static void r600_query_hw_emit_stop(struct r600_common_context *ctx,
882 ctx->need_gfx_cs_space(&ctx->b, query->num_cs_dw_end, false);
888 query->ops->emit_stop(ctx, query, query->buffer.buf, va);
893 ctx->num_cs_dw_queries_suspend -= query->num_cs_dw_end;
895 r600_update_occlusion_query_state(ctx, query->b.type, -1);
896 r600_update_prims_generated_query_state(ctx, query->b.type, -1);
899 static void emit_set_predicate(struct r600_common_context *ctx,
903 struct radeon_cmdbuf *cs = &ctx->gfx.cs;
908 r600_emit_reloc(ctx, &ctx->gfx, buf, RADEON_USAGE_READ |
912 static void r600_emit_query_predication(struct r600_common_context *ctx,
915 struct r600_query_hw *query = (struct r600_query_hw *)ctx->render_cond;
923 invert = ctx->render_cond_invert;
924 flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
925 ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
961 emit_set_predicate(ctx, qbuf->buf, va + 32 * stream, op);
967 emit_set_predicate(ctx, qbuf->buf, va, op);
976 static struct pipe_query *r600_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
979 (struct r600_common_screen *)ctx->screen;
989 static void r600_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
991 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
997 static bool r600_begin_query(struct pipe_context *ctx,
1000 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1054 static bool r600_end_query(struct pipe_context *ctx, struct pipe_query *query)
1056 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1298 static bool r600_get_query_result(struct pipe_context *ctx,
1302 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1308 static void r600_get_query_result_resource(struct pipe_context *ctx,
1316 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1752 static void r600_render_condition(struct pipe_context *ctx,
1757 struct r600_common_context *rctx = (struct r600_common_context *)ctx;
1779 void r600_suspend_queries(struct r600_common_context *ctx)
1783 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1784 r600_query_hw_emit_stop(ctx, query);
1786 assert(ctx->num_cs_dw_queries_suspend == 0);
1789 static unsigned r600_queries_num_cs_dw_for_resuming(struct r600_common_context *ctx,
1807 num_dw += ctx->streamout.enable_atom.num_dw;
1814 void r600_resume_queries(struct r600_common_context *ctx)
1817 unsigned num_cs_dw = r600_queries_num_cs_dw_for_resuming(ctx, &ctx->active_queries);
1819 assert(ctx->num_cs_dw_queries_suspend == 0);
1822 ctx->need_gfx_cs_space(&ctx->b, num_cs_dw, true);
1824 LIST_FOR_EACH_ENTRY(query, &ctx->active_queries, list) {
1825 r600_query_hw_emit_start(ctx, query);
1832 struct r600_common_context *ctx =
1834 struct radeon_cmdbuf *cs = &ctx->gfx.cs;
1840 if (ctx->family == CHIP_JUNIPER) {
1848 ctx->screen->info.max_render_backends = 8;
1850 max_rbs = ctx->screen->info.max_render_backends;
1862 (ctx->gfx_level < EVERGREEN || rscreen->info.r600_gb_backend_map != 0)) {
1867 if (ctx->gfx_level >= EVERGREEN) {
1890 pipe_buffer_create(ctx->b.screen, 0,
1896 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_MAP_WRITE);
1906 r600_emit_reloc(ctx, &ctx->gfx, buffer,
1910 results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_MAP_READ);