Lines Matching refs:state
324 const struct pipe_blend_state *state, int mode)
336 if (state->logicop_enable) {
337 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
342 if (state->independent_blend_enable) {
344 target_mask |= (state->rt[i].colormask << (4 * i));
348 target_mask |= (state->rt[0].colormask << (4 * i));
353 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
355 blend->alpha_to_one = state->alpha_to_one;
365 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
378 /* state->rt entries > 0 only written if independent blending */
379 const int j = state->independent_blend_enable ? i : 0;
381 unsigned eqRGB = state->rt[j].rgb_func;
382 unsigned srcRGB = state->rt[j].rgb_src_factor;
383 unsigned dstRGB = state->rt[j].rgb_dst_factor;
384 unsigned eqA = state->rt[j].alpha_func;
385 unsigned srcA = state->rt[j].alpha_src_factor;
386 unsigned dstA = state->rt[j].alpha_dst_factor;
391 if (!state->rt[j].blend_enable) {
413 const struct pipe_blend_state *state)
416 return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
420 const struct pipe_depth_stencil_alpha_state *state)
431 dsa->valuemask[0] = state->stencil[0].valuemask;
432 dsa->valuemask[1] = state->stencil[1].valuemask;
433 dsa->writemask[0] = state->stencil[0].writemask;
434 dsa->writemask[1] = state->stencil[1].writemask;
435 dsa->zwritemask = state->depth_writemask;
437 db_depth_control = S_028800_Z_ENABLE(state->depth_enabled) |
438 S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
439 S_028800_ZFUNC(state->depth_func);
442 if (state->stencil[0].enabled) {
444 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
445 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
446 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
447 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
449 if (state->stencil[1].enabled) {
451 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
452 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
453 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
454 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
461 if (state->alpha_enabled) {
462 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha_func);
464 alpha_ref = fui(state->alpha_ref_value);
475 const struct pipe_rasterizer_state *state)
488 rs->scissor_enable = state->scissor;
489 rs->clip_halfz = state->clip_halfz;
490 rs->flatshade = state->flatshade;
491 rs->sprite_coord_enable = state->sprite_coord_enable;
492 rs->rasterizer_discard = state->rasterizer_discard;
493 rs->two_side = state->light_twoside;
494 rs->clip_plane_enable = state->clip_plane_enable;
495 rs->pa_sc_line_stipple = state->line_stipple_enable ?
496 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
497 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
499 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
500 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
501 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
503 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard);
504 rs->multisample_enable = state->multisample;
507 rs->offset_units = state->offset_units;
508 rs->offset_scale = state->offset_scale * 16.0f;
509 rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri;
510 rs->offset_units_unscaled = state->offset_units_unscaled;
512 if (state->point_size_per_vertex) {
513 psize_min = util_get_min_point_size(state);
517 psize_min = state->point_size;
518 psize_max = state->point_size;
527 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
533 tmp = r600_pack_float_12p4(state->point_size/2);
540 S_028A08_WIDTH((unsigned)(state->line_width * 8)));
544 S_028A48_MSAA_ENABLE(state->multisample) |
546 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
550 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
554 S_028C08_PIX_CENTER_HALF(state->half_pixel_center) |
558 r600_store_context_reg(&rs->buffer, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
560 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
561 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
562 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
563 S_028814_FACE(!state->front_ccw) |
564 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
565 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
566 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
567 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
568 state->fill_back != PIPE_POLYGON_MODE_FILL) |
569 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
570 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
575 const struct pipe_sampler_state *state)
580 : state->max_anisotropy;
582 bool trunc_coord = state->min_img_filter == PIPE_TEX_FILTER_NEAREST &&
583 state->mag_img_filter == PIPE_TEX_FILTER_NEAREST;
584 float max_lod = state->max_lod;
594 if (state->min_mip_filter == PIPE_TEX_MIPFILTER_NONE)
595 max_lod = state->min_lod;
597 ss->border_color_use = sampler_state_needs_border_color(state);
601 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
602 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
603 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
604 S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
605 S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
606 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
608 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
612 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
616 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
617 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
622 memcpy(&ss->border_color, &state->border_color, sizeof(state->border_color));
914 const struct pipe_sampler_view *state,
928 view->base = *state;
935 if (state->target == PIPE_BUFFER)
939 params.pipe_format = state->format;
943 params.first_level = state->u.tex.first_level;
944 params.last_level = state->u.tex.last_level;
945 params.first_layer = state->u.tex.first_layer;
946 params.last_layer = state->u.tex.last_layer;
947 params.target = state->target;
948 params.swizzle[0] = state->swizzle_r;
949 params.swizzle[1] = state->swizzle_g;
950 params.swizzle[2] = state->swizzle_b;
951 params.swizzle[3] = state->swizzle_a;
961 if (state->format == PIPE_FORMAT_X24S8_UINT ||
962 state->format == PIPE_FORMAT_S8X24_UINT ||
963 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
964 state->format == PIPE_FORMAT_S8_UINT)
975 const struct pipe_sampler_view *state)
977 return evergreen_create_sampler_view_custom(ctx, tex, state,
1011 struct pipe_clip_state *state = &rctx->clip_state.state;
1014 radeon_emit_array(cs, (unsigned*)state, 6*4);
1018 const struct pipe_poly_stipple *state)
1444 const struct pipe_framebuffer_state *state)
1451 /* Flush TC when changing the framebuffer state, because the only
1463 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1466 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1467 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1468 util_format_is_pure_integer(state->cbufs[0]->format);
1470 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1472 for (i = 0; i < state->nr_cbufs; i++) {
1473 surf = (struct r600_surface*)state->cbufs[i];
1481 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1496 /* Update alpha-test state dependencies.
1498 if (state->nr_cbufs) {
1502 surf = (struct r600_surface*)state->cbufs[0];
1519 if (state->zsbuf) {
1520 surf = (struct r600_surface*)state->zsbuf;
1522 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1528 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1529 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1544 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
1547 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1551 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1576 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1577 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1578 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1581 if (state->zsbuf) {
1709 struct r600_image_state *state = (struct r600_image_state *)atom;
1710 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
1717 struct r600_image_view *image = &state->views[i];
1839 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1840 unsigned nr_cbufs = state->nr_cbufs;
1854 cb = (struct r600_surface*)state->cbufs[i];
1905 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1918 if (state->zsbuf) {
1919 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
1922 (struct r600_resource*)state->zsbuf->texture,
1958 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1975 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a;
1976 float offset_units = state->offset_units;
1977 float offset_scale = state->offset_scale;
1980 if (!state->offset_units_unscaled) {
1981 switch (state->zs_format) {
2121 struct r600_vertexbuf_state *state,
2126 uint32_t dirty_mask = state->dirty_mask;
2134 vb = &state->vb[buffer_index];
2163 state->dirty_mask = 0;
2178 struct r600_constbuf_state *state,
2185 uint32_t dirty_mask = state->dirty_mask;
2194 cb = &state->cb[buffer_index];
2237 state->dirty_mask = 0;
2333 struct r600_samplerview_state *state,
2337 uint32_t dirty_mask = state->dirty_mask;
2344 rview = state->views[resource_index];
2362 state->dirty_mask = 0;
2547 struct r600_cso_state *state = (struct r600_cso_state*)a;
2548 struct r600_fetch_shader *shader = (struct r600_fetch_shader*)state->cso;
2564 struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a;
2573 if (state->geom_enable) {
2652 if (!state->geom_enable)
2668 struct r600_gs_rings_state *state = (struct r600_gs_rings_state*)a;
2675 if (state->enable) {
2676 rbuffer =(struct r600_resource*)state->esgs_ring.buffer;
2684 state->esgs_ring.buffer_size >> 8);
2686 rbuffer =(struct r600_resource*)state->gsvs_ring.buffer;
2694 state->gsvs_ring.buffer_size >> 8);
3334 /* Pull any state we use out of rctx. Make sure that any additional
3335 * state added to this list is also checked in the caller in
3863 /* emit reloc before writing cs so that cs is always in consistent state */
4351 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
4355 cb = &state->cb[slot];
4677 /* transition back to dyn gpr enabled state */