Lines Matching refs:rtex
173 static unsigned r600_tex_dim(struct r600_texture *rtex,
176 unsigned res_target = rtex->resource.b.b.target;
1117 struct r600_texture *rtex,
1132 color->offset = (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
1136 color->offset += rtex->resource.gpu_address;
1140 pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
1141 slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
1147 switch (rtex->surface.u.legacy.level[level].mode) {
1155 non_disp_tiling = rtex->non_disp_tiling;
1159 non_disp_tiling = rtex->non_disp_tiling;
1162 tile_split = rtex->surface.u.legacy.tile_split;
1163 macro_aspect = rtex->surface.u.legacy.mtilea;
1164 bankw = rtex->surface.u.legacy.bankw;
1165 bankh = rtex->surface.u.legacy.bankh;
1166 if (rtex->fmask.size)
1167 fmask_bankh = rtex->fmask.bank_height;
1169 fmask_bankh = rtex->surface.u.legacy.bankh;
1199 if (rtex->resource.b.b.nr_samples > 1) {
1200 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1224 do_endian_swap = !rtex->db_compatible;
1256 if (rtex->fmask.size) {
1280 if (rtex->fmask.size) {
1281 color->fmask = (rtex->resource.gpu_address + rtex->fmask.offset) >> 8;
1282 color->fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1325 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1329 evergreen_set_color_surface_common(rctx, rtex, level,
1357 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1359 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
1368 offset = rtex->resource.gpu_address;
1369 offset += (uint64_t)rtex->surface.u.legacy.level[level].offset_256B * 256;
1371 switch (rtex->surface.u.legacy.level[level].mode) {
1381 tile_split = rtex->surface.u.legacy.tile_split;
1382 macro_aspect = rtex->surface.u.legacy.mtilea;
1383 bankw = rtex->surface.u.legacy.bankw;
1384 bankh = rtex->surface.u.legacy.bankh;
1399 if (rscreen->b.gfx_level == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1400 surf->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1413 if (rtex->surface.has_stencil) {
1415 unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
1419 stencil_offset = (uint64_t)rtex->surface.u.legacy.zs.stencil_level[level].offset_256B * 256;
1420 stencil_offset += rtex->resource.gpu_address;
1430 if (r600_htile_enabled(rtex, level)) {
1431 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset;
1448 struct r600_texture *rtex;
1479 rtex = (struct r600_texture*)surf->base.texture;
1491 if (rtex->fmask.size) {
1712 struct r600_texture *rtex;
1728 rtex = (struct r600_texture *)image->base.resource;
1730 rtex = NULL;
1756 radeon_emit(cs, rtex ? rtex->cmask.base_address_reg : image->cb_color_base); /* R_028C7C_CB_COLOR0_CMASK */
1757 radeon_emit(cs, rtex ? rtex->cmask.slice_tile_max : 0); /* R_028C80_CB_COLOR0_CMASK_SLICE */
1760 radeon_emit(cs, rtex ? rtex->color_clear_value[0] : 0); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
1761 radeon_emit(cs, rtex ? rtex->color_clear_value[1] : 0); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2051 struct r600_texture *rtex = (struct r600_texture *)a->rsurf->base.texture;
2054 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2058 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
4213 struct r600_texture *rtex = (struct r600_texture *)image;
4214 if (!is_buffer & rtex->db_compatible)
4219 if (!is_buffer && rtex->cmask.size)
4225 evergreen_set_color_surface_common(rctx, rtex,