Lines Matching refs:rsrc
3780 struct r600_texture *rsrc = (struct r600_texture*)src;
3788 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3804 slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
3811 height = u_minify(rsrc->resource.b.b.height0, src_level);
3816 base = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
3820 bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
3821 bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
3822 mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
3823 tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
3824 base += rsrc->resource.gpu_address;
3842 addr = (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
3843 addr += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_z;
3850 addr += rsrc->resource.gpu_address;
3855 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3864 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3894 struct r600_texture *rsrc = (struct r600_texture*)src;
3917 dstz, rsrc, src_level, src_box))
3927 src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
3928 src_w = u_minify(rsrc->resource.b.b.width0, src_level);
3930 copy_height = src_box->height / rsrc->surface.blk_h;
3933 src_mode = rsrc->surface.u.legacy.level[src_level].mode;
3964 src_offset= (uint64_t)rsrc->surface.u.legacy.level[src_level].offset_256B * 256;
3965 src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;