Lines Matching refs:rctx
477 struct r600_context *rctx = (struct r600_context *)ctx;
548 if (rctx->b.gfx_level == CAYMAN) {
637 static void evergreen_fill_buffer_resource_words(struct r600_context *rctx,
684 texture_buffer_sampler_view(struct r600_context *rctx,
701 evergreen_fill_buffer_resource_words(rctx, view->base.texture,
707 list_addtail(&view->list, &rctx->texture_buffers);
724 static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
730 struct r600_screen *rscreen = (struct r600_screen*)rctx->b.b.screen;
773 format = r600_translate_texformat(rctx->b.b.screen, params->pipe_format,
918 struct r600_context *rctx = (struct r600_context*)ctx;
936 return texture_buffer_sampler_view(rctx, view, width0, height0);
953 ret = evergreen_fill_tex_resource_words(rctx, texture, ¶ms,
981 static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom)
983 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
988 radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs));
1008 static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom)
1010 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1011 struct pipe_clip_state *state = &rctx->clip_state.state;
1022 static void evergreen_get_scissor_rect(struct r600_context *rctx,
1028 evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor);
1048 static void evergreen_set_color_surface_buffer(struct r600_context *rctx,
1059 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1066 format = r600_translate_colorformat(rctx->b.gfx_level, pformat, FALSE);
1116 static void evergreen_set_color_surface_common(struct r600_context *rctx,
1124 struct r600_screen *rscreen = rctx->screen;
1195 if (rctx->b.gfx_level == CAYMAN) {
1226 format = r600_translate_colorformat(rctx->b.gfx_level, pformat, do_endian_swap);
1294 void evergreen_init_color_surface_rat(struct r600_context *rctx,
1300 evergreen_set_color_surface_buffer(rctx, (struct r600_resource *)surf->base.texture,
1322 void evergreen_init_color_surface(struct r600_context *rctx,
1329 evergreen_set_color_surface_common(rctx, rtex, level,
1353 static void evergreen_init_depth_surface(struct r600_context *rctx,
1356 struct r600_screen *rscreen = rctx->screen;
1446 struct r600_context *rctx = (struct r600_context *)ctx;
1455 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE |
1463 util_copy_framebuffer_state(&rctx->framebuffer.state, state);
1466 rctx->framebuffer.export_16bpc = state->nr_cbufs != 0;
1467 rctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1469 rctx->framebuffer.compressed_cb_mask = 0;
1470 rctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1484 evergreen_init_color_surface(rctx, surf);
1488 rctx->framebuffer.export_16bpc = false;
1492 rctx->framebuffer.compressed_cb_mask |= 1 << i;
1508 if (rctx->alphatest_state.bypass != alphatest_bypass) {
1509 rctx->alphatest_state.bypass = alphatest_bypass;
1510 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1512 if (rctx->alphatest_state.cb0_export_16bpc != export_16bpc) {
1513 rctx->alphatest_state.cb0_export_16bpc = export_16bpc;
1514 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1525 evergreen_init_depth_surface(rctx, surf);
1528 if (state->zsbuf->format != rctx->poly_offset_state.zs_format) {
1529 rctx->poly_offset_state.zs_format = state->zsbuf->format;
1530 r600_mark_atom_dirty(rctx, &rctx->poly_offset_state.atom);
1533 if (rctx->db_state.rsurf != surf) {
1534 rctx->db_state.rsurf = surf;
1535 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1536 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1538 } else if (rctx->db_state.rsurf) {
1539 rctx->db_state.rsurf = NULL;
1540 r600_mark_atom_dirty(rctx, &rctx->db_state.atom);
1541 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1544 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs ||
1545 rctx->cb_misc_state.bound_cbufs_target_mask != target_mask) {
1546 rctx->cb_misc_state.bound_cbufs_target_mask = target_mask;
1547 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1548 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1551 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1552 rctx->alphatest_state.bypass = false;
1553 r600_mark_atom_dirty(rctx, &rctx->alphatest_state.atom);
1556 log_samples = util_logbase2(rctx->framebuffer.nr_samples);
1558 if ((rctx->b.gfx_level == CAYMAN ||
1559 rctx->b.family == CHIP_RV770) &&
1560 rctx->db_misc_state.log_samples != log_samples) {
1561 rctx->db_misc_state.log_samples = log_samples;
1562 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
1567 rctx->framebuffer.atom.num_dw = 4; /* SCISSOR */
1570 if (rctx->b.gfx_level == EVERGREEN)
1571 rctx->framebuffer.atom.num_dw += 17; /* Evergreen */
1573 rctx->framebuffer.atom.num_dw += 28; /* Cayman */
1576 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23;
1577 rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2;
1578 rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3;
1582 rctx->framebuffer.atom.num_dw += 24;
1583 rctx->framebuffer.atom.num_dw += 2;
1585 rctx->framebuffer.atom.num_dw += 4;
1588 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1590 r600_set_sample_locations_constant_buffer(rctx);
1591 rctx->framebuffer.do_update_surf_dirtiness = true;
1596 struct r600_context *rctx = (struct r600_context *)ctx;
1598 if (rctx->ps_iter_samples == min_samples)
1601 rctx->ps_iter_samples = min_samples;
1602 if (rctx->framebuffer.nr_samples > 1) {
1603 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
1659 static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, int ps_iter_samples)
1662 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1706 static void evergreen_emit_image_state(struct r600_context *rctx, struct r600_atom *atom,
1710 struct pipe_framebuffer_state *fb_state = &rctx->framebuffer.state;
1711 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1722 idx += fb_state->nr_cbufs + (rctx->dual_src_blend ? 1 : 0);
1732 reloc = radeon_add_to_buffer_list(&rctx->b,
1733 &rctx->b.gfx,
1738 immed_reloc = radeon_add_to_buffer_list(&rctx->b,
1739 &rctx->b.gfx,
1804 static void evergreen_emit_fragment_image_state(struct r600_context *rctx, struct r600_atom *atom)
1806 evergreen_emit_image_state(rctx, atom,
1811 static void evergreen_emit_compute_image_state(struct r600_context *rctx, struct r600_atom *atom)
1813 evergreen_emit_image_state(rctx, atom,
1819 static void evergreen_emit_fragment_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1821 int offset = util_bitcount(rctx->fragment_images.enabled_mask);
1822 evergreen_emit_image_state(rctx, atom,
1827 static void evergreen_emit_compute_buffer_state(struct r600_context *rctx, struct r600_atom *atom)
1829 int offset = util_bitcount(rctx->compute_images.enabled_mask);
1830 evergreen_emit_image_state(rctx, atom,
1836 static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r600_atom *atom)
1838 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
1839 struct pipe_framebuffer_state *state = &rctx->framebuffer.state;
1862 reloc = radeon_add_to_buffer_list(&rctx->b,
1863 &rctx->b.gfx,
1871 cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
1905 if (rctx->framebuffer.dual_src_blend && i == 1 && state->cbufs[0]) {
1910 i += util_bitcount(rctx->fragment_images.enabled_mask);
1911 i += util_bitcount(rctx->fragment_buffers.enabled_mask);
1920 unsigned reloc = radeon_add_to_buffer_list(&rctx->b,
1921 &rctx->b.gfx,
1958 evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1964 if (rctx->b.gfx_level == EVERGREEN) {
1965 evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples);
1967 cayman_emit_msaa_state(cs, rctx->framebuffer.nr_samples,
1968 rctx->ps_iter_samples, 0);
1972 static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600_atom *a)
1974 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2012 uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a,
2030 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2032 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2036 unsigned rat_colormask = evergreen_construct_rat_mask(rctx, a, a->nr_cbufs);
2045 static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom *atom)
2047 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2058 reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource,
2068 static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
2070 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2078 if (rctx->b.num_occlusion_queries > 0 &&
2081 if (rctx->b.gfx_level == CAYMAN) {
2093 if (rctx->alphatest_state.sx_alpha_test_control)
2120 static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
2125 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2160 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2166 static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2168 evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_FS, 0);
2171 static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
2173 evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, EG_FETCH_CONSTANTS_OFFSET_CS,
2177 static void evergreen_emit_constant_buffers(struct r600_context *rctx,
2184 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2206 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2232 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2241 static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2243 if (rctx->vs_shader->current->shader.vs_as_ls) {
2244 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2250 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX],
2258 static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2260 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY],
2267 static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2269 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT],
2276 static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2278 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE],
2286 static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2288 if (!rctx->tes_shader)
2290 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL],
2297 static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2299 if (!rctx->tes_shader)
2301 evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL],
2308 void evergreen_setup_scratch_buffers(struct r600_context *rctx) {
2323 struct r600_pipe_shader *stage = rctx->hw_shader_stages[i].shader;
2326 r600_setup_scratch_area_for_shader(rctx, stage,
2327 &rctx->scratch_buffers[i], regs[i].ring_base, regs[i].item_size, regs[i].ring_size);
2332 static void evergreen_emit_sampler_views(struct r600_context *rctx,
2336 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2351 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rview->tex_resource,
2365 static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2367 if (rctx->vs_shader->current->shader.vs_as_ls) {
2368 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2371 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views,
2376 static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2378 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views,
2382 static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2384 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views,
2388 static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2390 if (!rctx->tes_shader)
2392 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views,
2396 static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2398 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views,
2402 static void evergreen_emit_cs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2404 evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views,
2439 static void evergreen_emit_sampler_states(struct r600_context *rctx,
2445 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2480 static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2482 if (rctx->vs_shader->current->shader.vs_as_ls) {
2483 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72,
2486 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18,
2491 static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2493 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY], 36,
2497 static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2499 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54,
2503 static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2505 if (!rctx->tes_shader)
2507 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18,
2511 static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2513 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0,
2517 static void evergreen_emit_cs_sampler_states(struct r600_context *rctx, struct r600_atom *atom)
2519 evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE], 90,
2524 static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2529 radeon_set_context_reg(&rctx->b.gfx.cs, R_028C3C_PA_SC_AA_MASK,
2533 static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2536 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2544 static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct r600_atom *a)
2546 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2556 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer,
2561 static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a)
2563 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2568 if (rctx->vs_shader->current->shader.vs_as_gs_a) {
2576 if (rctx->gs_shader->gs_max_out_vertices <= 128)
2578 else if (rctx->gs_shader->gs_max_out_vertices <= 256)
2580 else if (rctx->gs_shader->gs_max_out_vertices <= 512)
2587 if (!rctx->tes_shader)
2593 if (rctx->gs_shader->current->shader.gs_prim_id_input)
2597 if (rctx->tes_shader) {
2599 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2649 if (rctx->tes_shader) {
2665 static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a)
2667 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
2680 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2690 radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer,
2728 static void cayman_init_atom_start_cs(struct r600_context *rctx)
2730 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2750 cayman_init_common_regs(cb, rctx->b.gfx_level,
2751 rctx->b.family, rctx->screen->b.info.drm_minor);
2865 if (rctx->screen->b.has_streamout) {
2887 void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb,
2911 rctx->default_gprs[R600_HW_STAGE_PS] = 93;
2912 rctx->default_gprs[R600_HW_STAGE_VS] = 46;
2913 rctx->r6xx_num_clause_temp_gprs = 4;
2914 rctx->default_gprs[R600_HW_STAGE_GS] = 31;
2915 rctx->default_gprs[R600_HW_STAGE_ES] = 31;
2916 rctx->default_gprs[EG_HW_STAGE_HS] = 23;
2917 rctx->default_gprs[EG_HW_STAGE_LS] = 23;
2957 void evergreen_init_atom_start_cs(struct r600_context *rctx)
2959 struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2976 if (rctx->b.gfx_level == CAYMAN) {
2977 cayman_init_atom_start_cs(rctx);
2998 evergreen_init_common_regs(rctx, cb, rctx->b.gfx_level,
2999 rctx->b.family, rctx->screen->b.info.drm_minor);
3001 family = rctx->b.family;
3275 if (rctx->screen->b.has_streamout) {
3290 if (rctx->b.family == CHIP_CAICOS) {
3315 struct r600_context *rctx = (struct r600_context *)ctx;
3334 /* Pull any state we use out of rctx. Make sure that any additional
3338 bool sprite_coord_enable = rctx->rasterizer ? rctx->rasterizer->sprite_coord_enable : 0;
3339 bool flatshade = rctx->rasterizer ? rctx->rasterizer->flatshade : 0;
3340 bool msaa = rctx->framebuffer.nr_samples > 1 && rctx->ps_iter_samples > 0;
3682 void *evergreen_create_resolve_blend(struct r600_context *rctx)
3689 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, V_028808_CB_RESOLVE);
3692 void *evergreen_create_decompress_blend(struct r600_context *rctx)
3695 unsigned mode = rctx->screen->has_compressed_msaa_texturing ?
3701 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3704 void *evergreen_create_fastclear_blend(struct r600_context *rctx)
3712 return evergreen_create_blend_state_mode(&rctx->b.b, &blend, mode);
3715 void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3719 return rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
3722 void evergreen_update_db_shader_control(struct r600_context * rctx)
3727 if (!rctx->ps_shader) {
3731 dual_export = rctx->framebuffer.export_16bpc &&
3732 !rctx->ps_shader->current->ps_depth_export;
3734 db_shader_control = rctx->ps_shader->current->db_shader_control |
3738 S_02880C_ALPHA_TO_MASK_DISABLE(rctx->framebuffer.cb0_is_integer);
3752 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) {
3758 if (db_shader_control != rctx->db_misc_state.db_shader_control) {
3759 rctx->db_misc_state.db_shader_control = db_shader_control;
3760 r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
3764 static void evergreen_dma_copy_tile(struct r600_context *rctx,
3779 struct radeon_cmdbuf *cs = &rctx->b.dma.cs;
3799 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
3855 r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource);
3864 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rsrc->resource,
3866 radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource,
3893 struct r600_context *rctx = (struct r600_context *)ctx;
3901 if (rctx->b.dma.cs.priv == NULL) {
3905 if (rctx->cmd_buf_is_compute) {
3906 rctx->b.gfx.flush(rctx, PIPE_FLUSH_ASYNC, NULL);
3907 rctx->cmd_buf_is_compute = false;
3911 evergreen_dma_copy_buffer(rctx, dst, src, dst_x, src_box->x, src_box->width);
3916 !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty,
3951 if ((rctx->b.gfx_level == CAYMAN) &&
3970 evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
3973 evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y, dst_z,
3988 struct r600_context *rctx = (struct r600_context *)ctx;
3990 memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4);
3991 memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2);
3992 rctx->driver_consts[PIPE_SHADER_TESS_CTRL].tcs_default_levels_dirty = true;
3997 struct r600_context *rctx = (struct r600_context *)ctx;
3999 rctx->patch_vertices = patch_vertices;
4002 static void evergreen_setup_immed_buffer(struct r600_context *rctx,
4006 struct r600_screen *rscreen = (struct r600_screen *)rctx->b.b.screen;
4023 evergreen_fill_buffer_resource_words(rctx, &resource->immed_buffer->b.b,
4033 struct r600_context *rctx = (struct r600_context *)ctx;
4037 astate = &rctx->atomic_buffer_state;
4064 struct r600_context *rctx = (struct r600_context *)ctx;
4078 istate = &rctx->fragment_buffers;
4080 istate = &rctx->compute_buffers;
4100 evergreen_setup_immed_buffer(rctx, rview, PIPE_FORMAT_R32_UINT);
4104 evergreen_set_color_surface_buffer(rctx, resource,
4135 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4146 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4149 if (rctx->cb_misc_state.buffer_rat_enabled_mask != istate->enabled_mask) {
4150 rctx->cb_misc_state.buffer_rat_enabled_mask = istate->enabled_mask;
4151 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4155 r600_mark_atom_dirty(rctx, &istate->atom);
4163 struct r600_context *rctx = (struct r600_context *)ctx;
4180 istate = &rctx->fragment_images;
4182 istate = &rctx->compute_images;
4210 evergreen_setup_immed_buffer(rctx, rview, iview->format);
4225 evergreen_set_color_surface_common(rctx, rtex,
4236 evergreen_set_color_surface_buffer(rctx, resource,
4298 evergreen_fill_tex_resource_words(rctx, &resource->b.b, &tex_params,
4311 evergreen_fill_buffer_resource_words(rctx, &resource->b.b,
4331 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV;
4332 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
4336 r600_mark_atom_dirty(rctx, &rctx->framebuffer.atom);
4338 if (rctx->cb_misc_state.image_rat_enabled_mask != istate->enabled_mask) {
4339 rctx->cb_misc_state.image_rat_enabled_mask = istate->enabled_mask;
4340 r600_mark_atom_dirty(rctx, &rctx->cb_misc_state.atom);
4344 r600_mark_atom_dirty(rctx, &istate->atom);
4347 static void evergreen_get_pipe_constant_buffer(struct r600_context *rctx,
4351 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
4361 static void evergreen_get_shader_buffers(struct r600_context *rctx,
4368 struct r600_image_state *istate = &rctx->compute_buffers;
4395 struct r600_context *rctx = (struct r600_context *)ctx;
4396 st->saved_compute = rctx->cs_shader_state.shader;
4399 evergreen_get_pipe_constant_buffer(rctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
4401 evergreen_get_shader_buffers(rctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
4405 void evergreen_init_state_functions(struct r600_context *rctx)
4418 if (rctx->b.gfx_level == EVERGREEN) {
4419 r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11);
4420 rctx->config_state.dyn_gpr_enabled = true;
4422 r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0);
4423 r600_init_atom(rctx, &rctx->fragment_images.atom, id++, evergreen_emit_fragment_image_state, 0);
4424 r600_init_atom(rctx, &rctx->compute_images.atom, id++, evergreen_emit_compute_image_state, 0);
4425 r600_init_atom(rctx, &rctx->fragment_buffers.atom, id++, evergreen_emit_fragment_buffer_state, 0);
4426 r600_init_atom(rctx, &rctx->compute_buffers.atom, id++, evergreen_emit_compute_buffer_state, 0);
4428 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0);
4429 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0);
4430 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0);
4431 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0);
4432 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0);
4433 r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0);
4435 r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0);
4437 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0);
4438 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0);
4439 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0);
4440 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0);
4441 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0);
4442 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0);
4444 r600_init_atom(rctx, &rctx->vertex_buffer_state.atom, id++, evergreen_fs_emit_vertex_buffers, 0);
4445 r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0);
4446 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0);
4447 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0);
4448 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0);
4449 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0);
4450 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0);
4451 r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0);
4453 r600_init_atom(rctx, &rctx->vgt_state.atom, id++, r600_emit_vgt_state, 10);
4455 if (rctx->b.gfx_level == EVERGREEN) {
4456 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, evergreen_emit_sample_mask, 3);
4458 r600_init_atom(rctx, &rctx->sample_mask.atom, id++, cayman_emit_sample_mask, 4);
4460 rctx->sample_mask.sample_mask = ~0;
4462 r600_init_atom(rctx, &rctx->alphatest_state.atom, id++, r600_emit_alphatest_state, 6);
4463 r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6);
4464 r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0);
4465 r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4);
4466 r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9);
4467 r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26);
4468 r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10);
4469 r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14);
4470 r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0);
4471 r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9);
4472 r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0);
4473 r600_add_atom(rctx, &rctx->b.scissors.atom, id++);
4474 r600_add_atom(rctx, &rctx->b.viewports.atom, id++);
4475 r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4);
4476 r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5);
4477 r600_add_atom(rctx, &rctx->b.render_cond_atom, id++);
4478 r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++);
4479 r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++);
4481 r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0);
4482 r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15);
4483 r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26);
4485 rctx->b.b.create_blend_state = evergreen_create_blend_state;
4486 rctx->b.b.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
4487 rctx->b.b.create_rasterizer_state = evergreen_create_rs_state;
4488 rctx->b.b.create_sampler_state = evergreen_create_sampler_state;
4489 rctx->b.b.create_sampler_view = evergreen_create_sampler_view;
4490 rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state;
4491 rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple;
4492 rctx->b.b.set_min_samples = evergreen_set_min_samples;
4493 rctx->b.b.set_tess_state = evergreen_set_tess_state;
4494 rctx->b.b.set_patch_vertices = evergreen_set_patch_vertices;
4495 rctx->b.b.set_hw_atomic_buffers = evergreen_set_hw_atomic_buffers;
4496 rctx->b.b.set_shader_images = evergreen_set_shader_images;
4497 rctx->b.b.set_shader_buffers = evergreen_set_shader_buffers;
4498 if (rctx->b.gfx_level == EVERGREEN)
4499 rctx->b.b.get_sample_position = evergreen_get_sample_position;
4501 rctx->b.b.get_sample_position = cayman_get_sample_position;
4502 rctx->b.dma_copy = evergreen_dma_copy;
4503 rctx->b.save_qbo_state = evergreen_save_qbo_state;
4505 evergreen_init_compute_state_functions(rctx);
4525 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
4528 struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader;
4529 struct r600_pipe_shader_selector *ls = rctx->vs_shader;
4530 unsigned num_tcs_input_cp = rctx->patch_vertices;
4540 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
4545 if (!rctx->tes_shader) {
4546 rctx->lds_alloc = 0;
4547 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4549 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4551 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4556 if (rctx->lds_alloc != 0 &&
4557 rctx->last_ls == ls &&
4558 rctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4559 rctx->last_tcs == tcs)
4564 if (rctx->tcs_shader) {
4583 output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0;
4602 rctx->lds_alloc = (lds_size | (num_waves << 14));
4604 rctx->last_ls = ls;
4605 rctx->last_tcs = tcs;
4606 rctx->last_num_tcs_input_cp = num_tcs_input_cp;
4611 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX,
4613 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL,
4615 rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL,
4619 uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx,
4625 if (!rctx->tes_shader)
4628 num_output_cp = rctx->tcs_shader ?
4629 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
4630 rctx->patch_vertices;
4633 S_028B58_HS_NUM_INPUT_CP(rctx->patch_vertices) |
4637 void evergreen_set_ls_hs_config(struct r600_context *rctx,
4644 void evergreen_set_lds_alloc(struct r600_context *rctx,
4653 bool evergreen_adjust_gprs(struct r600_context *rctx)
4659 unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs;
4667 def_gprs[i] = rctx->default_gprs[i];
4673 if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) {
4674 if (rctx->config_state.dyn_gpr_enabled)
4678 rctx->config_state.dyn_gpr_enabled = true;
4679 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4680 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4687 if (rctx->hw_shader_stages[i].shader)
4688 num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr;
4693 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4694 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4695 cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4696 cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2);
4697 cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4698 cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3);
4716 if (rctx->config_state.dyn_gpr_enabled) {
4718 rctx->config_state.dyn_gpr_enabled = false;
4752 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4753 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4754 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4755 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4756 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4757 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];
4764 r600_mark_atom_dirty(rctx, &rctx->config_state.atom);
4765 rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE;
4772 void eg_trace_emit(struct r600_context *rctx)
4774 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4777 if (rctx->b.gfx_level < EVERGREEN)
4781 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4782 (struct r600_resource*)rctx->trace_buf, RADEON_USAGE_WRITE |
4785 rctx->trace_id++;
4786 radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rctx->trace_buf,
4789 radeon_emit(cs, rctx->trace_buf->gpu_address);
4790 radeon_emit(cs, rctx->trace_buf->gpu_address >> 32 | MEM_WRITE_32_BITS | MEM_WRITE_CONFIRM);
4791 radeon_emit(cs, rctx->trace_id);
4796 radeon_emit(cs, AC_ENCODE_TRACE_POINT(rctx->trace_id));
4799 static void evergreen_emit_set_append_cnt(struct r600_context *rctx,
4804 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4805 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4822 static void evergreen_emit_event_write_eos(struct r600_context *rctx,
4827 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4830 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4849 static void cayman_emit_event_write_eos(struct r600_context *rctx,
4854 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4856 uint32_t reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4875 static void cayman_write_count_to_gds(struct r600_context *rctx,
4880 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4881 unsigned reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
4897 void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx,
4913 pshader = rctx->hw_shader_stages[i].shader;
4941 void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx,
4946 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4963 if (rctx->b.gfx_level == CAYMAN)
4964 cayman_write_count_to_gds(rctx, atomic, resource, pkt_flags);
4966 evergreen_emit_set_append_cnt(rctx, atomic, resource, pkt_flags);
4970 void evergreen_emit_atomic_buffer_save(struct r600_context *rctx,
4975 struct radeon_cmdbuf *cs = &rctx->b.gfx.cs;
4976 struct r600_atomic_buffer_state *astate = &rctx->atomic_buffer_state;
4996 if (rctx->b.gfx_level == CAYMAN)
4997 cayman_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
4999 evergreen_emit_event_write_eos(rctx, atomic, resource, pkt_flags);
5005 ++rctx->append_fence_id;
5006 reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx,
5007 r600_resource(rctx->append_fence),
5010 dst_offset = r600_resource(rctx->append_fence)->gpu_address;
5015 radeon_emit(cs, rctx->append_fence_id);
5023 radeon_emit(cs, rctx->append_fence_id);