Lines Matching refs:info
828 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1035 unsigned info;
1059 MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
1097 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1098 color->info |= S_028C70_FORMAT(format) |
1146 color->info = 0;
1150 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1154 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1158 color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1180 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
1248 color->info |= S_028C70_FORMAT(format) |
1257 color->info |= S_028C70_COMPRESSION(1);
1273 color->info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1306 surf->cb_color_info = color.info | S_028C70_RAT(1);
1342 surf->cb_color_info = color.info;
1389 nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
2599 struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info;
2600 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
2601 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
2602 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
2603 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
2751 rctx->b.family, rctx->screen->b.info.drm_minor);
2999 rctx->b.family, rctx->screen->b.info.drm_minor);
3425 if (shader->selector->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3427 S_02880C_EXEC_ON_NOOP(shader->selector->info.writes_memory);
3428 } else if (shader->selector->info.writes_memory) {
3752 if (rctx->alphatest_state.sx_alpha_test_control || rctx->ps_shader->info.writes_memory) {
3799 nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
4007 uint32_t immed_size = rscreen->b.info.max_se * 256 * 64 * util_format_get_blocksize(pformat);
4114 rview->cb_color_info = color.info |
4273 rview->cb_color_info = color.info |
4525 void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches)
4540 unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes;
4566 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
4620 const struct pipe_draw_info *info,
4629 rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :