Lines Matching defs:tmp
478 unsigned tmp, spi_interp;
533 tmp = r600_pack_float_12p4(state->point_size/2);
535 S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
643 struct r600_texture *tmp = (struct r600_texture*)buffer;
661 va = tmp->resource.gpu_address + params->offset;
688 struct r600_texture *tmp = (struct r600_texture*)view->base.texture;
704 view->tex_resource = &tmp->resource;
706 if (tmp->resource.gpu_address)
731 struct r600_texture *tmp = (struct r600_texture*)texture;
743 tile_split = tmp->surface.u.legacy.tile_split;
744 surflevel = tmp->surface.u.legacy.level;
747 if (tmp->db_compatible) {
763 tile_split = tmp->surface.u.legacy.stencil_tile_split;
764 surflevel = tmp->surface.u.legacy.zs.stencil_level;
771 do_endian_swap = !tmp->db_compatible;
800 non_disp_tiling = tmp->non_disp_tiling;
814 macro_aspect = tmp->surface.u.legacy.mtilea;
815 bankw = tmp->surface.u.legacy.bankw;
816 bankh = tmp->surface.u.legacy.bankh;
821 fmask_bankh = eg_bank_wh(tmp->fmask.bank_height);
831 va = tmp->resource.gpu_address;
834 dim = r600_tex_dim(tmp, params->target, texture->nr_samples);
860 if (tmp->is_depth) {
866 tex_resource_words[3] = (tmp->fmask.offset + va) >> 8;
907 S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible);
920 struct r600_texture *tmp = (struct r600_texture*)texture;
967 view->tex_resource = &tmp->resource;
2901 unsigned tmp;
2919 tmp = 0;
2928 tmp |= S_008C00_VC_ENABLE(1);
2931 tmp |= S_008C00_EXPORT_SRC_C(1);
2932 tmp |= S_008C00_CS_PRIO(cs_prio);
2933 tmp |= S_008C00_LS_PRIO(ls_prio);
2934 tmp |= S_008C00_HS_PRIO(hs_prio);
2935 tmp |= S_008C00_PS_PRIO(ps_prio);
2936 tmp |= S_008C00_VS_PRIO(vs_prio);
2937 tmp |= S_008C00_GS_PRIO(gs_prio);
2938 tmp |= S_008C00_ES_PRIO(es_prio);
2941 r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2974 unsigned tmp, i;
3147 tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
3148 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
3149 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
3150 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
3153 r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
3155 tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
3156 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
3157 r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
3159 tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
3160 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
3161 r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
3163 tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
3164 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
3165 r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
3167 tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
3168 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
3169 r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
3330 unsigned spi_baryc_cntl = 0, sid, tmp, num = 0;
3385 tmp = S_028644_SEMANTIC(sid);
3389 tmp |= S_028644_DEFAULT_VAL(3);
3394 tmp |= S_028644_FLAT_SHADE(1);
3400 tmp |= S_028644_PT_SPRITE_TEX(1);
3403 spi_ps_input_cntl[num++] = tmp;
3600 unsigned i, tmp, nparams = 0;
3604 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3605 spi_vs_out_id[nparams / 4] |= tmp;
4663 unsigned tmp[3];
4742 tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) |
4746 tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) |
4749 tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) |
4752 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4753 rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] ||
4754 rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) {
4755 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
4756 rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1];
4757 rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2];